公开(公告)号：US10971225B2

公开(公告)日：2021-04-06

申请号：US16535712

申请日：2019-08-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kikuko Sugimae ,  Yusuke Arayashiki

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

公开(公告)号：US10546896B2

公开(公告)日：2020-01-28

申请号：US15696875

申请日：2017-09-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yusuke Arayashiki ,  Kouji Matsuo

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer. The storage device further includes a first variable resistance layer provided between the first and fifth conductive layers, a second variable resistance layer provided between the second and fifth conductive layers, a third variable resistance layer provided between the third and fifth conductive layers, and a fourth variable resistance layer provided between the first and sixth conductive layers. A first distance between the first and second variable resistance layers is shorter than a second distance between a portion of the first conductive layer and a portion of the second conductive layer which face each other across a region between the fifth and sixth conductive layers.

公开(公告)号：US09941006B1

公开(公告)日：2018-04-10

申请号：US15460600

申请日：2017-03-16

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yusuke Arayashiki

IPC: G11C5/06 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0069 ,  G11C11/5614 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/71 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145

Abstract: A memory device includes a first interconnect extending in a first direction, a second interconnect extending in a second direction crossing the first direction, a third interconnect extending in a third direction crossing a plane including the first direction and the second direction, a fourth interconnect extending in the third direction, a semiconductor member, a first resistance change film, and a second resistance change film. The semiconductor member is connected between a first end of the second interconnect and the first interconnect. The first resistance change film is connected between a side surface of the second interconnect and the third interconnect. The second resistance change film is connected between a second end of the second interconnect and the fourth interconnect.

公开(公告)号：US10410717B2

公开(公告)日：2019-09-10

申请号：US15265067

申请日：2016-09-14

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kikuko Sugimae ,  Yusuke Arayashiki

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

公开(公告)号：US09985205B2

公开(公告)日：2018-05-29

申请号：US15061328

申请日：2016-03-04

Applicant: Toshiba Memory Corporation

Inventor： Yusuke Arayashiki

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/118

CPC classification number: H01L45/145 ,  G11C2207/105 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/148 ,  H01L45/16 ,  H01L2027/11885 ,  H01L2027/11887 ,  H01L2224/05553 ,  H01L2224/05554

Abstract: According to one embodiment, a semiconductor memory device includes first and second interconnect parts, and a second interconnect connection part. The first interconnect part includes a first core part, and a first interconnect layer. The first interconnect layer includes a first surrounding region and a first extended region. The second interconnect part includes a second core part, and a second interconnect layer. The second interconnect layer includes a second surrounding region and a second extended region. The second extended connection part overlaps a part of the first extended region in the third direction, overlaps the second core part in the first direction, and is electrically connected to the second core part. The second extended surrounding part is provided around the second extended connection part and contains a material contained in the first surrounding region.

公开(公告)号：US10224374B2

公开(公告)日：2019-03-05

申请号：US15697388

申请日：2017-09-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kana Hirayama ,  Kazuhiko Yamamoto ,  Yusuke Arayashiki ,  Yosuke Murakami ,  Yusuke Kobayashi

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: According to one or more embodiments, a memory device includes a first interconnection extending in a first direction, a plurality of second interconnections extending in a second direction intersecting the first direction, and a first resistance change film provided between the first interconnection and the second interconnections. The first resistance change film includes a first conductive layer having a first conductivity, and a second conductive layer provided between the first conductive layer and the plurality of second interconnections and having a second conductivity higher than the first conductivity.

公开(公告)号：US09779808B2

公开(公告)日：2017-10-03

申请号：US15262575

申请日：2016-09-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yusuke Arayashiki ,  Kikuko Sugimae ,  Reika Ichihara

IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/004 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/71 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146

Abstract: A resistance random access memory device includes a control circuit. The control circuit applies a first voltage between the plurality of second interconnects and one of the first interconnects for a first time when switching resistance states of the variable resistance members from a first state to a second state, and the control circuit applies a second voltage between the plurality of second interconnects and the one of the first interconnects for a second time after applying the first voltage when the resistance state of one or more of the variable resistance members of a plurality of the variable resistance members connected to the one of the first interconnects is in the first state. The second voltage has the same polarity as the first voltage and is lower than the first voltage. The second time is longer than the first time.

公开(公告)号：US10804325B2

公开(公告)日：2020-10-13

申请号：US16129249

申请日：2018-09-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yosuke Murakami ,  Yusuke Arayashiki ,  Kazuhiko Yamamoto

IPC: H01L27/24 ,  H01L45/00

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a first signal line, a first conductive layer, a first storage layer and a first insulation layer. The first signal line extends in a first direction crossing the substrate. The first conductive layer extends in a second direction crossing the first direction and being parallel to the substrate, and has a first surface and a second surface that is away from the first signal line in a third direction crossing the first and second directions. The first storage layer is provided between the first signal line and the first conductive layer. The first insulation layer is provided between the second surface and the first storage layer.

公开(公告)号：US10734449B2

公开(公告)日：2020-08-04

申请号：US16289651

申请日：2019-02-28

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yusuke Arayashiki ,  Nobuyuki Momo ,  Motohiko Fujimatsu ,  Akira Hokazono

IPC: H01L27/24 ,  H01L45/00

Abstract: A storage device includes: a substrate; a first conductive layer extending in a first direction; a second conductive layer adjacent to the first conductive layer in a second direction, and extending in the first direction; a third conductive layer extending in a third direction; a fourth conductive layer extending in the second direction; a fifth conductive layer disposed on the second conductive layer, extending in the third direction, and being electrically connected to the fourth conductive layer; a first storage layer disposed between the third conductive layer and the fourth conductive layer; a first semiconductor layer disposed between the first conductive layer and the third conductive layer; a second semiconductor layer disposed between the second conductive layer and the fifth conductive layer; and a first gate electrode extending in the second direction and being shared by side surfaces of the first semiconductor layer and the second semiconductor layer.

公开(公告)号：US10727277B2

公开(公告)日：2020-07-28

申请号：US16279971

申请日：2019-02-19

Applicant: Toshiba Memory Corporation

Inventor： Yosuke Murakami ,  Takeshi Ishizaki ,  Yusuke Arayashiki ,  Kazuhiko Yamamoto ,  Kana Hirayama

IPC: G11C11/00 ,  H01L27/24 ,  H01L45/00

Abstract: A storage device includes a first conductor, a resistance variable film, and a second conductor. The resistance variable film includes a first layer and a second layer. The second layer is located on a side opposite to the first conductor with respect to the first layer, contains oxygen, and has conductivity higher than that of the first layer. The second conductor includes a first portion and a second portion. The first portion abuts on the second layer of the resistance variable film. The second portion is separated from the resistance variable film as compared to the first portion. The oxygen content of the first portion is higher than that of the second portion.