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Patent Agency Ranking
公开(公告)号：US09372227B2
公开(公告)日：2016-06-21
申请号：US13792323
申请日：2013-03-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Wei-Hsun Lin , Hao Chen , Chung-Han Huang
CPC classification number: G01R31/2889 , G01R31/2884
Abstract: A system for testing a device under test (DUT) includes a probe card and a test module. The probe card includes probe beds electrically coupled to a circuit board and a first plurality of electrical contacts coupled to the circuit board, which are for engaging respective ones of a plurality of electrical contacts of a test equipment module. Probes are coupled to respective probe beds and are disposed to engage electrical contacts of the DUT. The probe card includes a second plurality of electrical contacts coupled to the circuit board. The first and second pluralities of contacts are mutually exclusive. The test module includes a memory, a processor, and a plurality of electrical contacts electrically coupled to respective ones of the second plurality of electrical contacts of the probe card. The circuit board includes a first electrical path for electrically coupling the test equipment module to the test module.
Abstract translation: 用于测试被测器件（DUT）的系统包括探针卡和测试模块。 探针卡包括电耦合到电路板的探针台和耦合到电路板的第一多个电触点，其用于接合测试设备模块的多个电触点中的相应的一个。 探针耦合到相应的探针台并且被设置成接合DUT的电触点。 探针卡包括耦合到电路板的第二多个电触点。 第一和第二个联系人是相互排斥的。 测试模块包括存储器，处理器和电耦合到探针卡的第二多个电触点中的相应电触头的多个电触头。 电路板包括用于将测试设备模块电耦合到测试模块的第一电路径。
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公开(公告)号：US20150168459A1
公开(公告)日：2015-06-18
申请号：US14132722
申请日：2013-12-18
Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
Inventor： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen , Chung-Han Huang
CPC classification number: G01R27/2605 , G01R31/2856
Abstract: A circuit that includes a stacked circuit layer, a plurality of test contact points and a comparator is disclosed. The stacked circuit layer includes a plurality of reference capacitors each having a reference capacitance. Each of the test contact points is electrically connecting to an under-test capacitor of an under-test module. The comparator compares the reference capacitance of one of the reference capacitors with an under-test capacitance of the under-test capacitor corresponding to one of the test contact points to measure a range of the under-test capacitance.
Abstract translation: 公开了一种包括堆叠电路层，多个测试接触点和比较器的电路。 叠层电路层包括各自具有参考电容的多个参考电容器。 每个测试接触点电连接到被测试模块的测试不足的电容器。 比较器将参考电容器之一的参考电容与对应于一个测试接点的欠压电容器的受测电容进行比较，以测量未测试电容的范围。
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公开(公告)号：US20150241508A1
公开(公告)日：2015-08-27
申请号：US14186107
申请日：2014-02-21
Applicant: Taiwan Semiconductor Manufacturing CO.,LTD.
Inventor： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen , Chung-Han Huang
CPC classification number: H01L22/14 , G01R31/2889
Abstract: A circuit is disclosed that includes a signal-forcing path, a discharging path, a contact probe, a monitoring probe and a switch module. The signal-forcing path is connected to a signal source. The discharging path is connected to a discharging voltage terminal. The contact probe contacts a pad module of an under-test device. The monitoring probe generates a monitored voltage associated with the pad module. The switch module is operated in a discharging mode to connect the contact probe to the discharging path when the monitored voltage does not reach a threshold voltage such that the under-test device is discharged and is operated in an operation mode to connect the contact probe to the signal-forcing path when the monitored voltage reaches the threshold voltage such that a signal generated by the signal source is forced to the under-test device.
Abstract translation: 公开了包括信号强制路径，放电路径，接触探针，监测探针和开关模块的电路。 信号强制路径连接到信号源。 放电路径连接到放电电压端子。 接触探针接触未测试装置的垫模块。 监测探头产生与焊盘模块相关的监控电压。 开关模块在放电模式下工作，当监控电压未达到阈值电压时，将接触探头连接到放电路径，使得被测设备被放电并且在操作模式下操作以将接触探针连接到 当监视的电压达到阈值电压时，信号强制路径使得由信号源产生的信号被强制到被测设备。
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公开(公告)号：US09640447B2
公开(公告)日：2017-05-02
申请号：US14186107
申请日：2014-02-21
Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
Inventor： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen , Chung-Han Huang
CPC classification number: H01L22/14 , G01R31/2889
Abstract: A circuit is disclosed that includes a signal-forcing path, a discharging path, a contact probe, a monitoring probe and a switch module. The signal-forcing path is connected to a signal source. The discharging path is connected to a discharging voltage terminal. The contact probe contacts a pad module of an under-test device. The monitoring probe generates a monitored voltage associated with the pad module. The switch module is operated in a discharging mode to connect the contact probe to the discharging path when the monitored voltage does not reach a threshold voltage such that the under-test device is discharged and is operated in an operation mode to connect the contact probe to the signal-forcing path when the monitored voltage reaches the threshold voltage such that a signal generated by the signal source is forced to the under-test device.
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公开(公告)号：US09606155B2
公开(公告)日：2017-03-28
申请号：US14132722
申请日：2013-12-18
Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
Inventor： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen , Chung-Han Huang
CPC classification number: G01R27/2605 , G01R31/2856
Abstract: A circuit includes a stacked circuit layer, a plurality of test contact points, and a comparator. The stacked circuit layer includes a plurality of reference capacitors each having a reference capacitance. Each of the test contact points is electrically connecting to an under-test capacitor of an under-test module. The comparator compares the reference capacitance of one of the reference capacitors with an under-test capacitance of the under-test capacitor corresponding to one of the test contact points to measure a range of the under-test capacitance.
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