公开(公告)号：US11030368B2

公开(公告)日：2021-06-08

申请号：US16881706

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheok-Kei Lei ,  Chi-Lin Liu ,  Hui-Zhong Zhuang ,  Zhe-Wei Jiang ,  Chi-Yu Lu ,  Yi-Hsin Ko

IPC: G06F30/327 ,  G06F30/392 ,  G06F30/398 ,  H01L23/52 ,  H01L23/522

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

公开(公告)号：US10691849B2

公开(公告)日：2020-06-23

申请号：US15907689

申请日：2018-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheok-Kei Lei ,  Chi-Lin Liu ,  Hui-Zhong Zhuang ,  Zhe-Wei Jiang ,  Chi-Yu Lu ,  Yi-Hsin Ko

IPC: G06F17/50 ,  G06F30/327 ,  H01L23/52 ,  H01L23/522 ,  G06F30/392 ,  G06F30/398

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

公开(公告)号：US20190229715A1

公开(公告)日：2019-07-25

申请号：US16372667

申请日：2019-04-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Lin Liu ,  Ting-Wei Chiang ,  Jerry Chang-Jui Kao ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Shang-Chih Hsieh ,  Che Min Huang

IPC: H03K3/3562 ,  H01L27/092 ,  G01R31/3185

CPC classification number: H03K3/35625 ,  G01R31/318541 ,  H01L27/092

Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch circuitry and the second clock inverter circuit are disposed on a third line that is in parallel with and spaced apart from the second line.

公开(公告)号：US10270432B2

公开(公告)日：2019-04-23

申请号：US15496575

申请日：2017-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Lin Liu ,  Ting-Wei Chiang ,  Jerry Chang-Jui Kao ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Shang-Chih Hsieh ,  Che Min Huang

IPC: H03K3/3562 ,  H01L27/092 ,  G01R31/3185

Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes master switch circuitry made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region. The flip-flop also includes slave switch circuitry operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch perimeter resides within the flip-flop region and is non-overlapping with the master switch perimeter.

公开(公告)号：US20190095552A1

公开(公告)日：2019-03-28

申请号：US15907689

申请日：2018-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheok-Kei LEI ,  Chi-Lin Liu ,  Hui-Zhong Zhuang ,  Zhe-Wei Jiang ,  Chi-Yu Lu ,  Yi-Hsin Ko

IPC: G06F17/50 ,  H01L23/52

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

公开(公告)号：US11734481B2

公开(公告)日：2023-08-22

申请号：US17321574

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheok-Kei Lei ,  Chi-Lin Liu ,  Hui-Zhong Zhuang ,  Zhe-Wei Jiang ,  Chi-Yu Lu ,  Yi-Hsin Ko

IPC: G06F30/327 ,  H01L23/52 ,  H01L23/522 ,  G06F30/392 ,  G06F30/398

CPC classification number: G06F30/327 ,  G06F30/392 ,  G06F30/398 ,  H01L23/52 ,  H01L23/5222

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

公开(公告)号：US20210271794A1

公开(公告)日：2021-09-02

申请号：US17321574

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheok-Kei Lei ,  Chi-Lin Liu ,  Hui-Zhong Zhuang ,  Zhe-Wei Jiang ,  Chi-Yu Lu ,  Yi-Hsin Ko

IPC: G06F30/327 ,  H01L23/52 ,  H01L23/522 ,  G06F30/392 ,  G06F30/398

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

公开(公告)号：US20180152175A1

公开(公告)日：2018-05-31

申请号：US15485595

申请日：2017-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chia LAI ,  Meng-Hung Shen ,  Chi-Lin Liu ,  Stefan Rusu ,  Yan-Hao Chen ,  Jerry Chang-Jui Kao

IPC: H03K3/012 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/356104

Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

公开(公告)号：US20170317666A1

公开(公告)日：2017-11-02

申请号：US15496575

申请日：2017-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Lin Liu ,  Ting-Wei Chiang ,  Jerry Chang-Jui Kao ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Shang-Chih Hsieh ,  Che Min Huang

IPC: H03K3/3562 ,  H01L27/092 ,  G01R31/3177

CPC classification number: H03K3/35625 ,  G01R31/318541 ,  H01L27/092

Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes master switch circuitry made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region. The flip-flop also includes slave switch circuitry operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch perimeter resides within the flip-flop region and is non-overlapping with the master switch perimeter.

公开(公告)号：US12003239B2

公开(公告)日：2024-06-04

申请号：US17976187

申请日：2022-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chia Lai ,  Meng-Hung Shen ,  Chi-Lin Liu ,  Stefan Rusu ,  Yan-Hao Chen ,  Jerry Chang-Jui Kao

IPC: H03K3/3562 ,  H03K3/012 ,  H03K3/0233 ,  H03K3/037 ,  H03K3/289 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/02332 ,  H03K3/0372 ,  H03K3/289 ,  H03K3/356104 ,  H03K3/3562 ,  H03K3/35625

Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.