公开(公告)号：US12074069B2

公开(公告)日：2024-08-27

申请号：US17831108

申请日：2022-06-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jerry Chang-Jui Kao ,  Hui-Zhong Zhuang ,  Li-Chung Hsu ,  Sung-Yen Yeh ,  Yung-Chen Chien ,  Jung-Chan Yang ,  Tzu-Ying Lin

IPC: H01L23/535 ,  H01L21/48 ,  H01L21/822 ,  H01L23/50

CPC classification number: H01L21/8221 ,  H01L21/4828 ,  H01L23/50 ,  H01L23/535

Abstract: A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height.

公开(公告)号：US11916074B2

公开(公告)日：2024-02-27

申请号：US17875060

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Peng ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Li-Chun Tien ,  Pin-Dai Sue ,  Wei-Cheng Lin

IPC: H01L21/70 ,  H01L27/092 ,  H03K17/687

CPC classification number: H01L27/092 ,  H03K17/6872

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

公开(公告)号：US11916058B2

公开(公告)日：2024-02-27

申请号：US17876909

申请日：2022-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Lun Chien ,  Po-Chun Wang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Li-Chun Tien

IPC: H01L27/02 ,  G06F30/392 ,  H01L23/522

CPC classification number: H01L27/0207 ,  G06F30/392 ,  H01L23/5226

Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

公开(公告)号：US11734481B2

公开(公告)日：2023-08-22

申请号：US17321574

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheok-Kei Lei ,  Chi-Lin Liu ,  Hui-Zhong Zhuang ,  Zhe-Wei Jiang ,  Chi-Yu Lu ,  Yi-Hsin Ko

IPC: G06F30/327 ,  H01L23/52 ,  H01L23/522 ,  G06F30/392 ,  G06F30/398

CPC classification number: G06F30/327 ,  G06F30/392 ,  G06F30/398 ,  H01L23/52 ,  H01L23/5222

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

公开(公告)号：US11574900B2

公开(公告)日：2023-02-07

申请号：US16910658

申请日：2020-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Liang Chen ,  Shun Li Chen ,  Li-Chun Tien ,  Ting Yu Chen ,  Hui-Zhong Zhuang

IPC: H01L27/02 ,  G06F30/392 ,  H01L27/092

Abstract: A method includes generating a layout diagram of a cell of an integrated circuit (IC), and storing the generated layout diagram on a non-transitory computer-readable medium. In the generating the layout diagram of the cell, a first active region is arranged inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is arranged inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region is arranged to overlap the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region.

公开(公告)号：US20220367637A1

公开(公告)日：2022-11-17

申请号：US17523033

申请日：2021-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Chung Chen ,  Tsung-Hsin Yu ,  Chung-Hui Chen ,  Hui-Zhong Zhuang ,  Ya Yun Liu

IPC: H01L29/10 ,  H01L27/088 ,  H01L29/08 ,  H01L21/8234

Abstract: The present disclosure describes structure with a substrate, a first well region, a second well region, and a third well region. The first well region is in the substrate. The second well region is in the first well region and includes a first source/drain (S/D) region. The third well region is in the substrate and adjacent to the first well region. The third well region includes a second S/D region, where a spacing between the first and second S/D regions is less than about 3 μm.

公开(公告)号：US11476250B2

公开(公告)日：2022-10-18

申请号：US17120839

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Peng ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Li-Chun Tien ,  Pin-Dai Sue ,  Wei-Cheng Lin

IPC: H01L21/70 ,  H01L27/092 ,  H03K17/687

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

公开(公告)号：US11239228B2

公开(公告)日：2022-02-01

申请号：US16921894

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Li-Chun Tien

IPC: G06F7/50 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  G06F30/392 ,  H01L27/118 ,  G06F111/20 ,  G06F119/18

Abstract: An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.

公开(公告)号：US20210271794A1

公开(公告)日：2021-09-02

申请号：US17321574

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheok-Kei Lei ,  Chi-Lin Liu ,  Hui-Zhong Zhuang ,  Zhe-Wei Jiang ,  Chi-Yu Lu ,  Yi-Hsin Ko

IPC: G06F30/327 ,  H01L23/52 ,  H01L23/522 ,  G06F30/392 ,  G06F30/398

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

公开(公告)号：US20200006338A1

公开(公告)日：2020-01-02

申请号：US16021847

申请日：2018-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei PENG ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Li-Chun Tien ,  Pin-Dai Sue ,  Wei-Cheng Lin

IPC: H01L27/092 ,  H03K17/687

Abstract: Exemplary embodiments of an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.