公开(公告)号：US20190258770A1

公开(公告)日：2019-08-22

申请号：US16404326

申请日：2019-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Lin Wu ,  Cheng-Cheng Kuo ,  Chia-Ping Chiang ,  Chih-Wei Hsu ,  Hua-Tai Lin ,  Kuei-Shun Chen ,  Yuan-Hsiang Lung ,  Yan-Tso Tsai

IPC: G06F17/50 ,  H01L21/308 ,  H01L21/027 ,  H01L21/306 ,  H01L27/02 ,  H01L27/118

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.

公开(公告)号：US20180174853A1

公开(公告)日：2018-06-21

申请号：US15474522

申请日：2017-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Chi-Cheng Hung ,  Chin-Hsiang Lin ,  Chien-Wei Wang ,  Ching-Yu Chang ,  Chih-Yuan Ting ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yuan-Hsiang Lung ,  Yen-Ming Chen ,  Yung-Sung Yen

IPC: H01L21/308 ,  H01L21/265 ,  H01L21/027

CPC classification number: H01L21/26586 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144

Abstract: A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.

公开(公告)号：US20180096090A1

公开(公告)日：2018-04-05

申请号：US15411613

申请日：2017-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Lin Wu ,  Cheng-Cheng Kuo ,  Chia-Ping Chiang ,  Chih-Wei Hsu ,  Hua-Tai Lin ,  Kuei-Shun Chen ,  Yuan-Hsiang Lung ,  Yan-Tso Tsai

IPC: G06F17/50 ,  H01L21/308 ,  H01L21/306 ,  H01L21/027

CPC classification number: G06F17/5072 ,  G06F17/504 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/0274 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.

公开(公告)号：US09754064B2

公开(公告)日：2017-09-05

申请号：US15286357

申请日：2016-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chuan-Fang Su ,  Kun-Zhi Chung ,  Yuan-Hsiang Lung

IPC: G06F17/50 ,  G06K9/76 ,  G03F1/36

CPC classification number: G06F17/5072 ,  G03F1/36 ,  G06F17/5081 ,  G06K9/76

Abstract: An IC design method includes: receiving a first layout including a first pattern; receiving a second layout including a second pattern, the first pattern separated from the second pattern when overlapping the first layout and the second layout; providing a cut pattern between the first pattern and the second pattern and overlapping the first pattern when overlapping the first layout, the second layout and the cut pattern; and providing a jog extending from the cut pattern to further overlap the first pattern with a length when a spacing between the second pattern and an edge of the cut pattern overlapping the first pattern is lower than a predetermined value, in which a ratio of the length of the jog to the spacing between the second pattern and the edge of the cut pattern overlapping the first pattern is in a range of 1/5 to 1/1.

公开(公告)号：US20200279743A1

公开(公告)日：2020-09-03

申请号：US16877755

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Chi-Cheng Hung ,  Chin-Hsiang Lin ,  Chien-Wei Wang ,  Ching-Yu Chang ,  Chih-Yuan Ting ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yuan-Hsiang Lung ,  Yen-Ming Chen ,  Yung-Sung Yen

IPC: H01L21/265 ,  H01L21/311 ,  H01L21/033

Abstract: A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.

公开(公告)号：US09477804B2

公开(公告)日：2016-10-25

申请号：US14600970

申请日：2015-01-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chuan-Fang Su ,  Kun-Zhi Chung ,  Yuan-Hsiang Lung

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G03F1/36 ,  G06F17/5081 ,  G06K9/76

Abstract: An IC design method includes: receiving a first layout including a first pattern; receiving a second layout including a second pattern, the first pattern separated from the second pattern when overlapping the first layout and the second layout; providing a cut pattern between the first pattern and the second pattern and overlapping the first pattern when overlapping the first layout, the second layout and the cut pattern; and providing a jog extending from the cut pattern to further overlap the first pattern with a length when a spacing between the second pattern and an edge of the cut pattern overlapping the first pattern is lower than a predetermined value, in which a ratio of the length of the jog to the spacing between the second pattern and the edge of the cut pattern overlapping the first pattern is in a range of 1/5 to 1/1.

Abstract translation: IC设计方法包括：接收包括第一图案的第一布局; 接收包括第二图案的第二布局，当与所述第一布局和所述第二布局重叠时，所述第一图案与所述第二图案分离; 在第一图案和第二图案之间提供切割图案，并在与第一布局，第二布局和切割图案重叠时与第一图案重叠; 以及当所述第二图案和所述切割图案的边缘之间的间隔与所述第一图案重叠时，提供从所述切割图案延伸到所述第一图案以使所述第一图案重叠的长度低于预定值，其中所述长度 第二图案与与第一图案重叠的切割图案的边缘之间的间距的偏移在1/5至1/1的范围内。

公开(公告)号：US11158509B2

公开(公告)日：2021-10-26

申请号：US16877755

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Chi-Cheng Hung ,  Chin-Hsiang Lin ,  Chien-Wei Wang ,  Ching-Yu Chang ,  Chih-Yuan Ting ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yuan-Hsiang Lung ,  Yen-Ming Chen ,  Yung-Sung Yen

IPC: H01L21/265 ,  H01L21/311 ,  H01L21/033

Abstract: A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.

公开(公告)号：US20210089697A1

公开(公告)日：2021-03-25

申请号：US17106602

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Lin Wu ,  Cheng-Cheng Kuo ,  Chia-Ping Chiang ,  Chih-Wei Hsu ,  Hua-Tai Lin ,  Kuei-Shun Chen ,  Yuan-Hsiang Lung ,  Yan-Tso Tsai

IPC: G06F30/392 ,  H01L27/02 ,  H01L27/118 ,  G06F30/398 ,  H01L21/027 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.

公开(公告)号：US10853552B2

公开(公告)日：2020-12-01

申请号：US16404326

申请日：2019-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Lin Wu ,  Cheng-Cheng Kuo ,  Chia-Ping Chiang ,  Chih-Wei Hsu ,  Hua-Tai Lin ,  Kuei-Shun Chen ,  Yuan-Hsiang Lung ,  Yan-Tso Tsai

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/3323 ,  G06F119/18 ,  H01L27/02 ,  H01L27/118 ,  H01L21/027 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.

公开(公告)号：US10658184B2

公开(公告)日：2020-05-19

申请号：US15474522

申请日：2017-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Chi-Cheng Hung ,  Chin-Hsiang Lin ,  Chien-Wei Wang ,  Ching-Yu Chang ,  Chih-Yuan Ting ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yuan-Hsiang Lung ,  Yen-Ming Chen ,  Yung-Sung Yen

IPC: H01L21/265 ,  H01L21/311 ,  H01L21/033

Abstract: A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.