ANTIREFLECTION MEMBER AND MANUFACTURE METHOD FOR THE SAME
    2.
    发明申请
    ANTIREFLECTION MEMBER AND MANUFACTURE METHOD FOR THE SAME 有权
    抗反射构件及其制造方法

    公开(公告)号:US20120162774A1

    公开(公告)日:2012-06-28

    申请号:US13394359

    申请日:2010-09-08

    Abstract: An antireflection member comprising an antireflection layer includes two adjacent layers with different refractive indices, the antireflection layer formed at least on a first surface of a support substrate, and one of the two adjacent layers with different refractive indices located farther from the support substrate is a first layer, and another of the two adjacent layers is a second layer, wherein the antireflection layer contains two or more kinds of particles of different constituent elements and one or more kinds of binders, and a ratio b/a is more than 1.10 and less than 1.45, where “a” denotes a length of the line segment A1A2 connecting two arbitrarily-selected points A1 and A2 located on an interface between said first layer and said second layer and apart from each other by a linear distance of 500 nm or more, and “b” denotes a length of a line formed by projecting the line segment A1A2 in a direction perpendicular to the first surface of the support substrate onto the interface between the first layer and the second layer.

    Abstract translation: 包括抗反射层的防反射构件包括具有不同折射率的两个相邻层,至少在支撑衬底的第一表面上形成抗反射层,并且位于离支撑衬底更远的不同折射率的两个相邻层之一是 第一层,并且两个相邻层中的另一层是第二层,其中抗反射层包含两种或更多种不同组成元素和一种或多种粘合剂的颗粒,并且比率b / a大于1.10以下 大于1.45,其中“a”表示连接位于所述第一层和所述第二层之间的界面上的两个任意选择的点A1和A2的线段A1A2的长度,并且彼此间隔500nm以上的直线距离 而“b”表示通过将线段A1A2沿垂直于支撑基板的第一表面的方向投影到t上而形成的线的长度 他在第一层和第二层之间进行界面。

    Semiconductor device and method for fabricating the same
    4.
    发明授权
    Semiconductor device and method for fabricating the same 失效
    半导体装置及其制造方法

    公开(公告)号:US07316959B2

    公开(公告)日:2008-01-08

    申请号:US11004836

    申请日:2004-12-07

    Abstract: The semiconductor device comprises a semiconductor layer 18 formed on an insulation layer 16, a gate electrode 22 formed on the semiconductor layer with a gate insulation film 20 formed therebetween, a source/drain region 24 formed on the semiconductor layer on both sides of the gate electrode, and a semiconductor region 14 buried in the insulation layer 16 in a region below the gate electrode. The surface scattering of the carriers and phonon scattering can be prevented while suppressing the short channel effect. Resultantly the semiconductor device can have high mobility and high speed.

    Abstract translation: 半导体器件包括形成在绝缘层16上的半导体层18,形成在半导体层上的栅电极22,其间形成有栅极绝缘膜20,形成在栅极两侧的半导体层上的源/漏区24 电极,以及在栅电极下方的区域中埋设在绝缘层16中的半导体区域14。 可以在抑制短通道效应的同时,防止载流子的表面散射和声子散射。 结果,半导体器件可以具有高移动性和高速度。

    Laminated polyester film
    7.
    发明授权
    Laminated polyester film 失效
    层压聚酯薄膜

    公开(公告)号:US06828010B2

    公开(公告)日:2004-12-07

    申请号:US10276261

    申请日:2002-12-13

    Abstract: Provided is a laminated polyester film, in which a laminated layer comprising two types of polyester resins having different glass transition points from each other is formed on at least one side of a base polyester film wherein the two types of polyester resins are composed of a polyester resin (A) having a glass transition point of from 60° C. to 100° C., and a polyester resin (B) having a glass transition point of from 0° C. to 60° C. and the polyester resin (B) contains a specified component, and a dicarboxylic acid component having a sulfonic acid metal base is set as a specified ratio of the entire dicarboxylic acid components in the polyester resins (A) and (B), satisfies adhesiveness to various types of coating materials which has conventionally been incompatible and, further, satisfies anti-blocking properties, transparency, scratch resistance and the other properties.

    Abstract translation: 提供一种叠层聚酯膜,其中在基础聚酯膜的至少一侧上形成包含彼此具有不同玻璃化转变点的两种类型的聚酯树脂的层压层,其中两种类型的聚酯树脂由聚酯 玻璃化转变点为60〜100℃的树脂(A)和玻璃化转变点为0℃〜60℃的聚酯树脂(B)和聚酯树脂(B )含有规定成分,将具有磺酸金属碱的二羧酸成分设定为聚酯树脂(A)和(B)中的二羧酸成分的全部比例,满足对各种类型的涂料的粘合性, 通常是不相容的,并且进一步满足防粘连性,透明性,耐擦伤性和其它性能。

    Process for producing N-glycyltyrosine and its crystal structure
    8.
    发明授权
    Process for producing N-glycyltyrosine and its crystal structure 失效
    生产N-甘氨酰酪氨酸的方法及其晶体结构

    公开(公告)号:US06197998B1

    公开(公告)日:2001-03-06

    申请号:US09289737

    申请日:1999-04-12

    CPC classification number: C07K5/06026 C07C233/47

    Abstract: Provided is a process for efficiently producing N-glycyltyrosine of high purity represented by the following formula: a salt thereof, or a solvate thereof, which comprises adding dropwise to an aqueous suspension of tyrosine or a salt thereof 2 equivalents or more of a haloacetyl halide and an aqueous solution of an inorganic base simultaneously in the presence or absence of an organic solvent, and subjecting the resulting N-haloacetyltyrosine to a reaction with an ammonium ion. Also provided are N-glycyl-L-tyrosine dehydrate having the crystal structures showing specific diffraction patterns in X-ray powder diffraction and processes for producing the same which are characterized by comprising crystallizing the dihydrate from an ethanol-water mixed solvent or water.

    Abstract translation: 本发明提供了一种有效生产下式的高效纯化N-甘氨酰酪氨酸的方法:其盐或其溶剂合物,其包括滴加酪氨酸水溶液或其盐2当量或更多的卤代乙酰卤 和无机碱的水溶液同时在有机溶剂的存在或不存在下进行,并将所得N-卤代乙酰基酪氨酸与铵离子反应。 还提供了具有在X射线粉末衍射中显示特定衍射图案的晶体结构的N-甘氨酰-L-酪氨酸脱水
    体及其制备方法,其特征在于包括从乙醇 - 水混合溶剂或水中结晶二水合物。

    Logic circuit with enhancement type FET and Schottky gate
    9.
    发明授权
    Logic circuit with enhancement type FET and Schottky gate 失效
    具有增强型FET和肖特基栅极的逻辑电路

    公开(公告)号:US5336949A

    公开(公告)日:1994-08-09

    申请号:US924948

    申请日:1992-08-05

    Applicant: Takashi Mimura

    Inventor: Takashi Mimura

    CPC classification number: H01L27/0605 H03K19/0952

    Abstract: A logic circuit comprising an inverter which includes a load element connected at its one end to a high-potential power supply, an enhancement type N-channel field-effect transistor having a Schottky gate, the transistor being connected at its drain to another end of the load element and at its source to a low-potential power supply, an input terminal, and a gate-current control unit having negative resistance characteristic, the unit being provided between the input terminal and a gate of the enhancement type N-channel field-effect transistor for controlling a gate current that flows through the enhancement type N-channel field-effect transistor.

    Abstract translation: 一种逻辑电路,包括一个反相器,该反相器包括一端与高电位电源相连的负载元件,具有肖特基栅极的增强型N沟道场效应晶体管,晶体管在其漏极连接到另一端 负载元件和其源极到低电位电源,输入端子和具有负电阻特性的栅极电流控制单元,该单元设置在输入端子和增强型N沟道场的栅极之间 - 用于控制流过增强型N沟道场效应晶体管的栅极电流的晶体管。

    Compound semiconductor device having nonalloyed ohmic contacts
    10.
    发明授权
    Compound semiconductor device having nonalloyed ohmic contacts 失效
    具有非合金欧姆接触的复合半导体器件

    公开(公告)号:US4961194A

    公开(公告)日:1990-10-02

    申请号:US455853

    申请日:1989-12-21

    CPC classification number: H01L29/452 H01L29/7787

    Abstract: An ohmic contact layer is provided between an n-GaAs/n-AlGaAs/undoped GaAs double-heterojunction structure and source/drain electrodes in a high electron mobility transistor. The ohmic contact layer comprises In.sub.x Ga.sub.1-x As or Ge. The ohmic contact layer has a function of considerably reducing a specific contact resistance of a barrier formed at an interface between the ohmic contact layer and the source and drain electrodes. Thereby, a nonalloyed ohmic contact is formed between the source and drain electrodes and source and drain regions formed in the undoped GaAs layer.

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