公开(公告)号：US10387584B1

公开(公告)日：2019-08-20

申请号：US14559566

申请日：2014-12-03

Applicant: The MathWorks, Inc.

Inventor： Katalin Maria Popovici ,  Rajiv Ghosh-Roy ,  Senthilkumar Manickavasagam ,  Wang Chen ,  Girish Venkataramani ,  Wei Zang ,  Abhijeet H. Gadkari ,  Matthew H. Fornero

IPC: G06F9/54 ,  G06F17/50

Abstract: A method may include receiving functional model information regarding a set of functional blocks associated with a functional model. The functional model may include a streaming algorithm for exchanging streaming data. The method may include receiving architectural model information regarding physical devices included in a target device from a hardware-software co-design platform. The physical devices may include a software based processing device and a hardware based processing device. The method may include mapping the functional blocks to the physical devices to allow the streaming data to be communicated between the software based processing device and the hardware based processing device. The method may include generating a streaming interface to model communication of the streaming data between the software based processing device and the hardware based processing device. The method may include generating computer code for implementing the functional model on the target device and outputting the computer code.

公开(公告)号：US09454627B1

公开(公告)日：2016-09-27

申请号：US14640543

申请日：2015-03-06

Applicant: The MathWorks, Inc.

Inventor： Girish Venkataramani ,  Kiran K. Kintali ,  Wei Zang ,  Wang Chen

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5022

Abstract: Systems and methods optimize hardware description generated from a graphical model automatically. The system may include an optimizer. The optimizer may add a serializer component and a deserializer component to the model. The serializer component may receive parallel data and may produce serial data. The serializer may introduce one or more idle cycles into the serial data being produced. The deserializer component may receive serial data and may produce parallel data. The serializer and deserializer components may receive and generate control signals. The control signals may include a valid signal for indicating valid data elements of the serial and parallel data, and a start the start signal for indicating the beginning of a new frame or cycle when constructing parallel data from serial data.

Abstract translation: 系统和方法自动优化从图形模型生成的硬件描述。 该系统可以包括优化器。 优化器可以向模型添加一个串行化器组件和一个解串器组件。 串行器组件可以接收并行数据并且可以产生串行数据。 串行器可能会在正在生成的串行数据中引入一个或多个空闲周期。 解串器组件可以接收串行数据并且可以产生并行数据。 串行器和解串器组件可以接收和产生控制信号。 控制信号可以包括用于指示串行和并行数据的有效数据元素的有效信号，以及当从串行数据构建并行数据时开始用于指示新帧或周期的开始的起始信号。