公开(公告)号：US20180033636A1

公开(公告)日：2018-02-01

申请号：US15221586

申请日：2016-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Po-Cheng Huang ,  Yi-Liang Liu ,  Wen-Chin Lin ,  Chun-Yi Wang ,  Chun-Yuan Wu

IPC: H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/31053 ,  H01L21/02065 ,  H01L21/32115 ,  H01L21/823431

Abstract: A method of fabricating a semiconductor structure is provided. A substrate surface is provided and a first layer is disposed on the substrate surface. A second layer covering the first layer is formed wherein the materials of the first layer and the second layer are different. A first polishing operation is performed on the second layer until a first polished surface exposing a portion of the first layer is obtained. A second polishing operation is performed on the first polished surface to obtain a second polished surface wherein an upper portion of the exposed portion of the first layer is removed. None of the substrate is exposed from the first polished surface and the second polished surface.

公开(公告)号：US20210273076A1

公开(公告)日：2021-09-02

申请号：US16802564

申请日：2020-02-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yang-Ju Lu ,  Chun-Yi Wang ,  Fu-Shou Tsai ,  Yong-Yi Lin ,  Ching-Yang Chuang ,  Wen-Chin Lin ,  Hsin-Kuo Hsu

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/02

Abstract: A method of forming a gate includes the following steps. A gate structure is formed on a substrate. An etch stop layer is formed on the gate structure and the substrate. A dielectric layer is formed to cover the etch stop layer. The dielectric layer is planarized to form a planarized top surface of the dielectric layer and expose a portion of the etch stop layer on the gate structure. An oxygen containing treatment is performed to form an oxygen containing layer on the exposed etch stop layer. A deposition process is performed to form an oxide layer covering the planarized top surface of the dielectric layer and the oxygen containing layer.