公开(公告)号：US09779998B2

公开(公告)日：2017-10-03

申请号：US15450037

申请日：2017-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Tsai ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823468 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

公开(公告)号：US20170221766A1

公开(公告)日：2017-08-03

申请号：US15450037

申请日：2017-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Tsai ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L21/8234 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823468 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

公开(公告)号：US09685520B1

公开(公告)日：2017-06-20

申请号：US15355032

申请日：2016-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shuo-Lin Hsu ,  Hsin-Ta Hsieh ,  Chun-Chia Chen ,  Chen-Chien Li ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L21/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66666

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first gate dielectric layer is formed in a first gate trench and a second gate dielectric layer is formed in a second gate trench. A first bottom barrier layer is formed on the first gate dielectric layer and the second gate dielectric layer. A first conductivity type work function layer is formed on the first bottom barrier layer. A first treatment to the first gate dielectric layer and/or a second treatment to the first bottom barrier layer on the first gate dielectric layer are performed before the step of forming the first conductivity type work function layer. The first treatment and the second treatment are used to modify threshold voltages of specific transistors, and thicknesses of work function layers formed subsequently may be modified for increasing the related process window accordingly.

公开(公告)号：US20250151384A1

公开(公告)日：2025-05-08

申请号：US18540852

申请日：2023-12-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shuo-Lin Hsu ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen

IPC: H01L27/088 ,  H01L21/308 ,  H01L21/8252 ,  H01L29/66 ,  H01L29/778

Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound semiconductor layer is formed on a first device region and a second device region of a substrate. A III-V compound barrier layer is formed on the III-V compound semiconductor layer. A lamination structure is formed on the III-V compound barrier layer. The lamination structure includes a p-type doped III-V compound layer and a first mask layer disposed thereon. A patterning process is performed to the lamination structure. A first portion of the lamination structure located above the first device region is patterned by the patterning process. A second portion of the lamination structure located above the second device region is removed by the patterning process. A thickness of the second portion of the lamination structure is greater than a thickness of the first portion of the lamination structure before the patterning process.

公开(公告)号：US09634002B1

公开(公告)日：2017-04-25

申请号：US15057079

申请日：2016-02-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Tsai ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L27/08 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L21/823468 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device and method of manufacturing the same are provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.