公开(公告)号：US20220367192A1

公开(公告)日：2022-11-17

申请号：US17337457

申请日：2021-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Ying Lai ,  Hsin-Yu Hsieh ,  Chang-Mao Wang ,  Chung-Yi Chiu

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/3213

Abstract: A method of forming a semiconductor device is disclosed. A substrate having a first device region and a second device region is provided. A metal nitride barrier layer is formed to cover the first device region and the second device region. A titanium layer is deposited on the metal nitride barrier layer. The titanium layer is selectively removed from the second device region, thereby exposing the metal nitride barrier layer in the second device region. The titanium layer in the first device region is transformed into a titanium nitride layer. The titanium nitride layer is a work function layer on the first device region.

公开(公告)号：US11488829B1

公开(公告)日：2022-11-01

申请号：US17337457

申请日：2021-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Ying Lai ,  Hsin-Yu Hsieh ,  Chang-Mao Wang ,  Chung-Yi Chiu

IPC: H01L21/28 ,  H01L21/3213 ,  H01L29/49

Abstract: A method of forming a semiconductor device is disclosed. A substrate having a first device region and a second device region is provided. A metal nitride barrier layer is formed to cover the first device region and the second device region. A titanium layer is deposited on the metal nitride barrier layer. The titanium layer is selectively removed from the second device region, thereby exposing the metal nitride barrier layer in the second device region. The titanium layer in the first device region is transformed into a titanium nitride layer. The titanium nitride layer is a work function layer on the first device region.

公开(公告)号：US20170294523A1

公开(公告)日：2017-10-12

申请号：US15095154

申请日：2016-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhen Wu ,  Chiu-Hsien Yeh ,  Po-Wen Su ,  Kuan-Ying Lai

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/304 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/66795 ,  H01L21/02603 ,  H01L21/28158 ,  H01L21/304 ,  H01L21/76897 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the substrate; patterning the first organic layer to form an opening; forming a second organic layer in the opening; and removing the first organic layer to form a patterned second organic layer on the substrate.

公开(公告)号：US20220069102A1

公开(公告)日：2022-03-03

申请号：US17523946

申请日：2021-11-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

公开(公告)号：US10777420B1

公开(公告)日：2020-09-15

申请号：US16286495

申请日：2019-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Ying Lai ,  Chang-Mao Wang ,  Hsin-Yu Hsieh

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L21/31 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/04 ,  H01L21/308

Abstract: A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.

公开(公告)号：US11929418B2

公开(公告)日：2024-03-12

申请号：US17524723

申请日：2021-11-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/423 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/76838 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/66545

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

公开(公告)号：US11881518B2

公开(公告)日：2024-01-23

申请号：US17523946

申请日：2021-11-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L29/4966 ,  H01L21/76838 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/66545

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

公开(公告)号：US20200273714A1

公开(公告)日：2020-08-27

申请号：US16286495

申请日：2019-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Ying Lai ,  Chang-Mao Wang ,  Hsin-Yu Hsieh

IPC: H01L21/311 ,  H01L21/768

Abstract: A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.

公开(公告)号：US20220077300A1

公开(公告)日：2022-03-10

申请号：US17524723

申请日：2021-11-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

公开(公告)号：US11205705B2

公开(公告)日：2021-12-21

申请号：US16205174

申请日：2018-11-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.