公开(公告)号：US20170018456A1

公开(公告)日：2017-01-19

申请号：US15207797

申请日：2016-07-12

Applicant: UNIVERSITY OF WINDSOR

Inventor： Sazzadur CHOWDHURY ,  HORST SCHMIDT

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/31 ,  H01L21/4857 ,  H01L23/145 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/5389

Abstract: An integrated circuit includes stacked benzocyclobutene layers and a circuit geometry comprising conductive electric traces and interconnects on and/or extending through the BCB layers. A first said BCB layer formed and partially cured state. A top surface masked with photoresist, and after exposure, etched selectively form through vias at locations corresponding to conductive interconnects of the circuit geometry associated with said first BCB layer. A further mask coating is applied and after exposure, conductive metal is deposited to infill vias and form the electric traces of the circuit geometry. Subsequent BCB layers are then likewise formed, etched masked and coated in the same manner.

Abstract translation: 集成电路包括堆叠的苯并环丁烯层和电路几何形状，其包括在BCB层上和/或延伸通过BCB层的导电电迹线和互连。 第一个说BCB层形成并部分固化的状态。 用光致抗蚀剂掩蔽的顶表面，并且在曝光之后，通过与对应于与所述第一BCB层相关联的电路几何形状的导电互连的位置处的通孔选择性地形成蚀刻。 施加另外的掩模涂层，并且在曝光之后，沉积导电金属以填充通孔并形成电路几何形状的电迹线。 随后的BCB层同样地形成，蚀刻掩模和以相同的方式涂覆。