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公开(公告)号：US09632138B2
公开(公告)日：2017-04-25
申请号：US14879597
申请日：2015-10-09
Applicant: UltraSoC Technologies Ltd.
IPC: G01R31/317 , G01R31/3177
CPC classification number: G01R31/31705 , G01R31/31725 , G01R31/31727 , G01R31/3177
Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.
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公开(公告)号：US20160033575A1
公开(公告)日：2016-02-04
申请号：US14879597
申请日：2015-10-09
Applicant: UltraSoC Technologies Ltd.
IPC: G01R31/317 , G01R31/3177
CPC classification number: G01R31/31705 , G01R31/31725 , G01R31/31727 , G01R31/3177
Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.
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公开(公告)号：US09188638B2
公开(公告)日：2015-11-17
申请号：US14251044
申请日：2014-04-11
Applicant: UltraSoC Technologies Ltd
IPC: G01R31/317 , G01R31/3177
CPC classification number: G01R31/31705 , G01R31/31725 , G01R31/31727 , G01R31/3177
Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.
Abstract translation: 一种在集成电路芯片上功能测试系统电路的方法，所述系统电路包括多个子电路，并且所述集成电路芯片还包括调试电路，所述调试电路包括可变电路。 该方法包括：在系统电路处，执行由执行并发动作的子电路的功能; 在可变性电路中，改变并行动作的相对定时，以增加系统电路的功能性能中的一个或多个错误的可能性; 并且在调试电路中，记录系统电路的功能性能中的一个或多个错误。
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Patent Agency Ranking
公开(公告)号：US20150226795A1
公开(公告)日：2015-08-13
申请号：US14251157
申请日：2014-04-11
Applicant: UltraSoC Technologies Ltd
Inventor： Andrew Brian Thomas Hopkins , Iain Craig Robertson
IPC: G01R31/3177 , G01R31/317
CPC classification number: G01R31/3177 , G01R31/31705 , G06F11/3648
Abstract: A method of validating functional testing of system circuitry on an integrated circuit chip, the system circuitry configured to perform a plurality of functions, the integrated circuit chip further comprising debugging circuitry under the control of a debug controller, the debugging circuitry comprising at least one debug unit. The method comprises: at the system circuitry, performing one of the plurality of functions; applying a debug configuration to the at least one debug unit; and at the at least one debug unit, monitoring for a characteristic in the system circuitry's performance of the one of the plurality of functions according to that debug configuration, and reporting to the debug controller.
Abstract translation: 一种验证集成电路芯片上的系统电路的功能测试的方法，所述系统电路被配置为执行多个功能，所述集成电路芯片还包括在调试控制器的控制下的调试电路，所述调试电路包括至少一个调试 单元。 该方法包括：在系统电路处执行多个功能之一; 将调试配置应用于所述至少一个调试单元; 以及在所述至少一个调试单元处，根据所述调试配置来监视所述系统电路中的所述多个功能中的一个的性能的特征，以及向所述调试控制器报告。
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公开(公告)号：US09424166B2
公开(公告)日：2016-08-23
申请号：US14251260
申请日：2014-04-11
Applicant: UltraSoC Technologies Ltd
Inventor： Andrew Brian Thomas Hopkins , Iain Craig Robertson
IPC: G06F11/00 , G06F11/36 , G01R31/317 , G01R31/3177
CPC classification number: G06F11/3656 , G01R31/31705 , G01R31/31721 , G01R31/31723 , G01R31/3177 , G06F11/36 , G06F11/3648
Abstract: An integrated circuit chip device comprising: system circuitry; debugging circuitry configured to debug the system circuitry, the debugging circuitry being segmented into zones; wherein the debugging circuitry comprises an interconnect fabric configured to route debug messages through a zone from a zone entry node of the interconnect fabric to a zone exit node of the interconnect fabric; and wherein the debugging circuitry is configured to, on receiving a debug message at a zone entry node that is shorter than a specified length, modify the debug message to form a modified debug message by increasing the length of the debug message to the specified length.
Abstract translation: 一种集成电路芯片装置，包括：系统电路; 调试电路被配置为调试系统电路，调试电路被分段成区域; 其中所述调试电路包括被配置为将调试消息通过区域从所述互连结构的区域入口节点路由到所述互连结构的区域出口节点的互连结构; 并且其中所述调试电路被配置为在接收到比指定长度短的区域入口节点处的调试消息时，通过将所述调试消息的长度增加到所述指定长度来修改所述调试消息以形成修改的调试消息。
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公开(公告)号：US20150268302A1
公开(公告)日：2015-09-24
申请号：US14251260
申请日：2014-04-11
Applicant: UltraSoC Technologies Ltd
Inventor： Andrew Brian Thomas Hopkins , Iain Craig Robertson
IPC: G01R31/317 , G01R31/3177
CPC classification number: G06F11/3656 , G01R31/31705 , G01R31/31721 , G01R31/31723 , G01R31/3177 , G06F11/36 , G06F11/3648
Abstract: An integrated circuit chip device comprising: system circuitry; debugging circuitry configured to debug the system circuitry, the debugging circuitry being segmented into zones; wherein the debugging circuitry comprises an interconnect fabric configured to route debug messages through a zone from a zone entry node of the interconnect fabric to a zone exit node of the interconnect fabric; and wherein the debugging circuitry is configured to, on receiving a debug message at a zone entry node that is shorter than a specified length, modify the debug message to form a modified debug message by increasing the length of the debug message to the specified length.
Abstract translation: 一种集成电路芯片装置，包括：系统电路; 调试电路被配置为调试系统电路，调试电路被分段成区域; 其中所述调试电路包括被配置为将调试消息通过区域从所述互连结构的区域入口节点路由到所述互连结构的区域出口节点的互连结构; 并且其中所述调试电路被配置为在接收到比指定长度短的区域入口节点处的调试消息时，通过将所述调试消息的长度增加到所述指定长度来修改所述调试消息以形成修改的调试消息。
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公开(公告)号：US09140753B2
公开(公告)日：2015-09-22
申请号：US14251157
申请日：2014-04-11
Applicant: UltraSoC Technologies Ltd
Inventor： Andrew Brian Thomas Hopkins , Iain Craig Robertson
IPC: G06F11/26 , G01R31/3177 , G01R31/317 , G06F11/36
CPC classification number: G01R31/3177 , G01R31/31705 , G06F11/3648
Abstract: A method of validating functional testing of system circuitry on an integrated circuit chip, the system circuitry configured to perform a plurality of functions, the integrated circuit chip further comprising debugging circuitry under the control of a debug controller, the debugging circuitry comprising at least one debug unit. The method comprises: at the system circuitry, performing one of the plurality of functions; applying a debug configuration to the at least one debug unit; and at the at least one debug unit, monitoring for a characteristic in the system circuitry's performance of the one of the plurality of functions according to that debug configuration, and reporting to the debug controller.
Abstract translation: 一种验证集成电路芯片上的系统电路的功能测试的方法，所述系统电路被配置为执行多个功能，所述集成电路芯片还包括在调试控制器的控制下的调试电路，所述调试电路包括至少一个调试 单元。 该方法包括：在系统电路处执行多个功能之一; 将调试配置应用于所述至少一个调试单元; 以及在所述至少一个调试单元处，根据所述调试配置来监视所述系统电路中的所述多个功能中的一个的性能的特征，以及向所述调试控制器报告。
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公开(公告)号：US20150226801A1
公开(公告)日：2015-08-13
申请号：US14251044
申请日：2014-04-11
Applicant: UltraSoC Technologies Ltd
IPC: G01R31/317 , G01R31/3177
CPC classification number: G01R31/31705 , G01R31/31725 , G01R31/31727 , G01R31/3177
Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.
Abstract translation: 一种在集成电路芯片上功能测试系统电路的方法，所述系统电路包括多个子电路，并且所述集成电路芯片还包括调试电路，所述调试电路包括可变电路。 该方法包括：在系统电路处，执行由执行并发动作的子电路的功能; 在可变性电路中，改变并行动作的相对定时，以增加系统电路的功能性能中的一个或多个错误的可能性; 并且在调试电路中，记录系统电路的功能性能中的一个或多个错误。
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