公开(公告)号：US20200168450A1

公开(公告)日：2020-05-28

申请号：US16203212

申请日：2018-11-28

Applicant: United Microelectronics Corp.

Inventor： Ko-Wei Lin ,  Kuan-Hsiang Chen ,  Hsin-Fu Huang ,  Chun-Ling Lin ,  Sheng-Yi Su ,  Pei-Hsun Kao

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768

Abstract: A method for fabricating interconnect of semiconductor device. The method includes providing a base substrate, having an inter-layer dielectric layer on top. A copper interconnect structure is formed in the inter-layer dielectric layer. A pre-sputter clean process is performed with hydrogen radicals on the copper interconnect structure. A degas process is sequentially performed on the copper interconnect structure. A cobalt cap layer is formed on the copper interconnect structure.

公开(公告)号：US20220320420A1

公开(公告)日：2022-10-06

申请号：US17844741

申请日：2022-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Yi-Syun Chou ,  Ko-Wei Lin ,  Pei-Hsun Kao ,  Wei Chen ,  Chia-Fu Cheng ,  Chun-Yao Yang ,  Chia-Chang Hsu

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

公开(公告)号：US20250089334A1

公开(公告)日：2025-03-13

申请号：US18379674

申请日：2023-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Chen-Ming Wang ,  Po-Ching Su ,  Pei-Hsun Kao ,  Ti-Bin Chen ,  Chun-Wei Yu ,  Chih-Chiang Wu

IPC: H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor includes a substrate. A gate structure is disposed on the substrate. A liner oxide contacts a side of the gate structure. A silicon oxide spacer contacts the liner oxide. An end of the silicon oxide spacer forms a kink profile. A silicon nitride spacer contacts the silicon oxide spacer and a tail of the silicon nitride spacer covers part of the kink profile. A stressor covers the silicon nitride spacer and the substrate.

公开(公告)号：US11856870B2

公开(公告)日：2023-12-26

申请号：US17844741

申请日：2022-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Yi-Syun Chou ,  Ko-Wei Lin ,  Pei-Hsun Kao ,  Wei Chen ,  Chia-Fu Cheng ,  Chun-Yao Yang ,  Chia-Chang Hsu

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.