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    LAYOUT OF INTEGRATED CIRCUIT
    2.
    发明申请
    LAYOUT OF INTEGRATED CIRCUIT 有权

    公开(公告)号：US20230096645A1

    公开(公告)日：2023-03-30

    申请号：US17715974

    申请日：2022-04-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ruei-Yau Chen ,  Wei-Jen Wang ,  Kun-Yuan Wu ,  Chien-Fu Chen ,  Chen-Hsien Hsu

    IPC: H01L27/02

    Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1≤D1−S, L2≤D2−S, and D1≠D2.

    Speed-up charge pump and phase-locked loop and method for operating the same
    4.
    发明授权
    Speed-up charge pump and phase-locked loop and method for operating the same 有权

    公开(公告)号：US11115033B1

    公开(公告)日：2021-09-07

    申请号：US17065414

    申请日：2020-10-07

    Applicant: United Microelectronics Corp.

    Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Ruei-Yau Chen ,  Yu-Lin Chen

    IPC: H03L7/089 ,  H03L7/099

    Abstract: A speed-up charge pump includes a first charge pump for receiving an up signal and a down signal in digital form to produce a first voltage control signal at an output node. Further, at least one speed-up phase detector includes a first circuit path to receive the up signal and delay the up signal by a predetermined delay as a delay up signal and operate the up signal and the delay up signal by AND logic into an auxiliary up signal; and a second circuit path to receive the down signal and delay the down signal by the predetermined delay as a delay down signal and operate the down signal and the delay down signal by AND logic into an auxiliary down signal. A second charge pump is respectively receiving the auxiliary up and down signals to produce a second voltage control signal also at the output node.

    Semiconductor structure and manufacturing method thereof
    5.
    发明公开
    Semiconductor structure and manufacturing method thereof 审中-公开

    公开(公告)号：US20240006405A1

    公开(公告)日：2024-01-04

    申请号：US17875430

    申请日：2022-07-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Lin ,  Chien-Hung Chen ,  Ruei-Yau Chen

    IPC: H01L27/02 ,  H01L27/118 ,  H01L21/8234

    CPC classification number: H01L27/0207 ,  H01L27/11807 ,  H01L21/823481 ,  H01L2027/11831

    Abstract: The invention provides a semiconductor structure, which comprises a first standard cell and a second standard cell located on a substrate, wherein an isolation region is included between the first standard cell and the second standard cell, a plurality of fin structures and a plurality of gates form a plurality of transistors, which are respectively located in the first standard cell and the second standard cell, and a plurality of single diffusion breaks (SDBs) located in the first standard cell and the second standard cell. A plurality of first dummy grooves in the first standard cell and the second standard cell, and a plurality of second dummy grooves in the isolation region, wherein some of the second dummy grooves overlap the first dummy grooves.

    LAYOUT OF INTEGRATED CIRCUIT
    6.
    发明申请
    LAYOUT OF INTEGRATED CIRCUIT 有权

    公开(公告)号：US20230095481A1

    公开(公告)日：2023-03-30

    申请号：US17517642

    申请日：2021-11-02

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ruei-Yau Chen ,  Wei-Jen Wang ,  Kun-Yuan Wu ,  Chien-Fu Chen ,  Chen-Hsien Hsu

    IPC: H01L27/02

    Abstract: An integrated circuit layout includes a first and a second standard cells abutting along a boundary line. The boundary line and a first active region of the first standard cell include a distance D1. A first gate line on the first active region protrudes from the first active region by a length L1. The boundary line and a second active region of the second standard cell include a distance D2. A second gate line on the second active region protrudes from the second active region by a length L2. Two first dummy gate lines and two second dummy gate lines are disposed at two sides of the first active region and the second active region and are away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1≤D1−S, L2≤D2−S, and D1≠D2.

    LAYOUT OF INTEGRATED CIRCUIT
    8.
    发明公开
    LAYOUT OF INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20240290771A1

    公开(公告)日：2024-08-29

    申请号：US18657811

    申请日：2024-05-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ruei-Yau Chen ,  Wei-Jen Wang ,  Kun-Yuan Wu ,  Chien-Fu Chen ,  Chen-Hsien Hsu

    IPC: H01L27/02

    CPC classification number: H01L27/0207

    Abstract: An integrated circuit layout includes an upper active region comprising a first edge and a second edge extending along a first direction and respectively adjacent to an upper cell boundary by a distance D3 and a distance D4. A first gate line is disposed on the upper active region, extends along a second direction, and protrudes from the first edge by a length L3. A second gate line is disposed on the upper active region, extends along the second direction, and protrudes from the second edge by a length L4. Two dummy gate lines respectively extend along the second direction and are disposed at two sides of the upper active region and away from the upper cell boundary by a distance S. The first direction and the second direction are perpendicular. The distances D3, D4, S and the lengths L3 and L4 have the relationships: L3≤D3−S, L4≤D4−S, and D3≠D4.

    Layout of integrated circuit
    9.
    发明授权
    Layout of integrated circuit 有权

    公开(公告)号：US11984442B2

    公开(公告)日：2024-05-14

    申请号：US17715974

    申请日：2022-04-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ruei-Yau Chen ,  Wei-Jen Wang ,  Kun-Yuan Wu ,  Chien-Fu Chen ,  Chen-Hsien Hsu

    IPC: H01L27/02

    CPC classification number: H01L27/0207

    Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1≤D1−S, L2≤D2−S, and D1≠D2.

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