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公开(公告)号：US11239243B2
公开(公告)日：2022-02-01
申请号：US16866573
申请日：2020-05-05
Inventor： Chih-Chieh Tsai , Pin-Hong Chen , Tzu-Chieh Chen , Tsun-Min Cheng , Yi-Wei Chen , Hsin-Fu Huang , Chi-Mao Hsu , Shih-Fang Tzou
IPC: H01L27/108
Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.
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公开(公告)号：US20200350317A1
公开(公告)日：2020-11-05
申请号：US16931397
申请日：2020-07-16
Inventor： Pin-Hong Chen , Tsun-Min Cheng , Chih-Chieh Tsai , Tzu-Chieh Chen , Kai-Jiun Chang , Chia-Chen Wu , Yi-An Huang , Yi-Wei Chen , Hsin-Fu Huang , Chi-Mao Hsu , Li-Wei Feng , Ying-Chiao Wang , Chung-Yen Feng
IPC: H01L27/108 , H01L23/532 , H01L23/522 , H01L21/285 , H01L23/528 , H01L21/768 , H01L49/02
Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
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公开(公告)号：US10756090B2
公开(公告)日：2020-08-25
申请号：US15922899
申请日：2018-03-15
Inventor： Pin-Hong Chen , Tsun-Min Cheng , Chih-Chieh Tsai , Tzu-Chieh Chen , Kai-Jiun Chang , Chia-Chen Wu , Yi-An Huang , Yi-Wei Chen , Hsin-Fu Huang , Chi-Mao Hsu , Li-Wei Feng , Ying-Chiao Wang , Chung-Yen Feng
IPC: H01L21/8242 , H01L27/108 , H01L23/532 , H01L23/522 , H01L21/285 , H01L23/528 , H01L21/768 , H01L49/02 , H01L21/02
Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
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公开(公告)号：US10312242B2
公开(公告)日：2019-06-04
申请号：US15986780
申请日：2018-05-22
Inventor： Tzu-Chieh Chen , Pin-Hong Chen , Chih-Chieh Tsai , Chia-Chen Wu , Yi-An Huang , Kai-Jiun Chang , Tsun-Min Cheng , Yi-Wei Chen
IPC: H01L23/31 , H01L27/108
Abstract: A semiconductor memory device is provided, and which includes a substrate, plural gates, plural plugs, a capacitor structure and a conducting cap layer. The gates are disposed within the substrate, and the plugs are disposed on the substrate, with each plug electrically connected to two sides of each gate on the substrate. The capacitor structure is disposed on the substrate, and the capacitor structure includes plural capacitors, with each capacitor electrically connected to the plugs respectively. The conducting cap layer covers the top surface and sidewalls of the capacitor structure. Also, the semiconductor memory device further includes an adhesion layer and an insulating layer. The adhesion layer covers the conducting cap layer and the capacitor structure, and the insulating layer covers the adhesion layer.
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公开(公告)号：US10276389B1
公开(公告)日：2019-04-30
申请号：US15987887
申请日：2018-05-23
Inventor： Chih-Chieh Tsai , Yi-Wei Chen , Pin-Hong Chen , Chih-Chien Liu , Tzu-Chieh Chen , Chun-Chieh Chiu , Tsun-Min Cheng , Kai-Jiun Chang , Chia-Chen Wu , Yi-An Huang
IPC: H01L21/8238 , H01L21/336 , H01L29/78 , H01L29/76 , H01L21/28 , H01L21/768 , H01L29/49 , H01L27/108
Abstract: A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a first metal silicon nitride layer on the silicon layer; performing an oxygen treatment process to form an oxide layer on the first metal silicon nitride layer; forming a second metal silicon nitride layer on the oxide layer; forming a conductive layer on the second metal silicon nitride layer; and patterning the conductive layer, the second metal silicon nitride layer, the oxide layer, the first metal silicon nitride layer, and the silicon layer to form a gate structure.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20180337187A1
公开(公告)日：2018-11-22
申请号：US16028364
申请日：2018-07-05
Inventor： Chih-Chieh Tsai , Pin-Hong Chen , Tzu-Chieh Chen , Tsun-Min Cheng , Yi-Wei Chen , Hsin-Fu Huang , Chi-Mao Hsu , Shih-Fang Tzou
IPC: H01L27/108
Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.
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公开(公告)号：US10043811B1
公开(公告)日：2018-08-07
申请号：US15627455
申请日：2017-06-20
Inventor： Chih-Chieh Tsai , Pin-Hong Chen , Tzu-Chieh Chen , Tsun-Min Cheng , Yi-Wei Chen , Hsin-Fu Huang , Chi-Mao Hsu , Shih-Fang Tzou
IPC: H01L27/108
Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.
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公开(公告)号：US09773789B1
公开(公告)日：2017-09-26
申请号：US15260292
申请日：2016-09-08
Inventor： Yi-Wei Chen , Tsun-Min Cheng , Chih-Chieh Tsai , Kai-Jiun Chang
IPC: H01L29/49 , H01L27/108
CPC classification number: H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10897
Abstract: A dynamic random access memory (DRAM) device includes a substrate, plural buried gates and plural bit lines. The buried gates are disposed in the substrate along a first trench extending along a first direction. The bit lines are disposed over the buried gates and extending along a second direction across the first direction. Each of the bit lines includes a multi-composition barrier layer, wherein the multi-composition barrier layer includes WSixNy with x and y being greater than 0 and the multi-composition barrier layer is silicon-rich at a bottom portion thereof and is nitrogen-rich at a top portion thereof.
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公开(公告)号：US20150004780A1
公开(公告)日：2015-01-01
申请号：US14490679
申请日：2014-09-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Tsun-Min Cheng , Min-Chuan Tsai , Chih-Chien Liu , Jen-Chieh Lin , Pei-Ying Li , Shao-Wei Wang , Mon-Sen Lin , Ching-Ling Lin
IPC: H01L29/49 , H01L21/8234
CPC classification number: H01L29/4966 , H01L21/82345 , H01L21/823842 , H01L21/823857 , H01L29/4232 , H01L29/435 , H01L29/51 , H01L29/66045 , H01L29/66545 , H01L29/78
Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.
Abstract translation: 位于基板上的金属栅极结构包括栅介质层，金属层和氮化铝钛金属层。 栅介质层位于衬底上。 金属层位于栅极电介质层上。 氮化铝钛金属层位于金属层上。
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公开(公告)号：US11251187B2
公开(公告)日：2022-02-15
申请号：US15712151
申请日：2017-09-22
Inventor： Pin-Hong Chen , Yi-Wei Chen , Tzu-Chieh Chen , Chih-Chieh Tsai , Chia-Chen Wu , Kai-Jiun Chang , Yi-An Huang , Tsun-Min Cheng
IPC: H01L27/108
Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.
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