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公开(公告)号：US20250096820A1
公开(公告)日：2025-03-20
申请号：US18960776
申请日：2024-11-26
Applicant: VIAVI Solutions Inc.
Inventor： Onur DIZDAR , Matthew David BROWN , Jiancao HOU , Chi-ming LEUNG , Ata SATTARZADEH HASHEMI , Yi Xien YAP
Abstract: A device may receive a downlink signal from a base station and may construct a frozen decode matrix for decoding frozen bits from data of the downlink signal. The device may construct a linear feedback shift register (LFSR) generator matrix for a component of scrambling sequence seed bits and may multiply the frozen decode matrix and the LFSR generator matrix to generate a mapping matrix for mapping a value of a scrambling sequence initialization vector that initializes a scrambler to the frozen bits. The device may determine an inverse matrix of the mapping matrix and may multiply the inverse matrix and the frozen decode matrix to obtain a final matrix. The device may utilize the final matrix to recover, from the data of the downlink signal, the scrambling sequence seed bits used to initialize the component and may perform actions based on the scrambling sequence seed bits.
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Patent Agency Ranking
2.发明公开公开(公告)号：US20240333311A1
公开(公告)日：2024-10-03
申请号：US18128707
申请日：2023-03-30
Applicant: VIAVI Solutions Inc.
Inventor： Onur DIZDAR , Matthew David BROWN , Jiancao HOU , Chi-ming LEUNG , Ata SATTARZADEH HASHEMI , Yi Xien YAP
CPC classification number: H03M13/2778 , H03M13/13 , H03M13/635
Abstract: A device may receive a downlink signal from a base station and may determine an input-output relation of polar encoding based on a vector of the downlink signal. The device may perform an interleaving operation with a matrix and the input-output relation to obtain an interleaved vector and may utilize rate matching with the interleaved vector to determine a scrambling sequence of the downlink signal. The device may utilize a reverse sequence generator with the scrambling sequence to determine a scrambling sequence initialization vector for the scrambling sequence and may perform one or more actions based on the scrambling sequence initialization vector.
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3.发明公开公开(公告)号：US20240349125A1
公开(公告)日：2024-10-17
申请号：US18299498
申请日：2023-04-12
Applicant: VIAVI SOLUTIONS Inc.
Inventor： Onur DIZDAR , Ata SATTARZADEH HASHEMI , Yi Xien YAP , Stephen WANG
CPC classification number: H04W28/18 , H04L1/0009
Abstract: A device may determine whether to utilize perfect channel state information at transmitter (CSIT) or imperfect CSIT, and may calculate, based on determining to utilize the perfect CSIT, a first power allocation, a first rate allocation, and a first precoder allocation for a private stream of a user device. The device may determine first parameters or second parameters for the first power allocation, the first rate allocation, and the first precoder allocation, and may generate a first transmit signal and a first data allocation based on the first power allocation, the first rate allocation, the first precoder allocation, and the first parameters or the second parameters. The device may provide the first transmit signal, with the first data allocation, to the user device via the private stream.
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公开(公告)号：US20240292428A1
公开(公告)日：2024-08-29
申请号：US18170322
申请日：2023-02-16
Applicant: VIAVI Solutions Inc.
Inventor： Matthew David BROWN , Onur DIZDAR , Jiancao HOU , Chi-ming LEUNG , Ata SATTARZADEH HASHEMI , Yi Xien YAP , Wei LI
IPC: H04W72/232 , H04L1/00
CPC classification number: H04W72/232 , H04L1/0038 , H04L1/0061
Abstract: In some implementations, a user equipment (UE) may perform a decoding of downlink control information (DCI) via a physical downlink control channel (PDCCH) based on: a detection, by the UE, of a UE-specific scrambling sequence and a radio network temporary identifier (RNTI) corresponding to the UE-specific scrambling sequence; and a skipping, by the UE, of a de-scrambling operation prior to the decoding of the DCI, wherein information regarding the UE-specific scrambling sequence and the RNTI is not previously stored by the UE. The UE may refrain from decoding a plurality of possible UE-specific scrambling sequences based on the skipping of the de-scrambling operation prior to the decoding of the DCI.
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公开(公告)号：US20250070802A1
公开(公告)日：2025-02-27
申请号：US18946175
申请日：2024-11-13
Applicant: VIAVI Solutions Inc.
Inventor： Onur DIZDAR , Matthew David BROWN , Jiancao HOU , Chi-ming LEUNG , Ata SATTARZADEH HASHEMI , Yi Xien YAP
Abstract: A device may receive a downlink signal from a base station and may determine an input-output relation of polar encoding based on a vector of the downlink signal. The device may perform an interleaving operation with a matrix and the input-output relation to obtain an interleaved vector and may utilize rate matching with the interleaved vector to determine a scrambling sequence of the downlink signal. The device may utilize a reverse sequence generator with the scrambling sequence to determine a scrambling sequence initialization vector for the scrambling sequence and may perform one or more actions based on the scrambling sequence initialization vector.
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6.发明公开公开(公告)号：US20240333313A1
公开(公告)日：2024-10-03
申请号：US18128725
申请日：2023-03-30
Applicant: VIAVI Solutions Inc.
Inventor： Onur DIZDAR , Matthew David BROWN , Jiancao HOU , Chi-ming LEUNG , Ata SATTARZADEH HASHEMI , Yi Xien YAP
CPC classification number: H03M13/2927 , H03M13/13 , H03M13/2778
Abstract: A device may receive a downlink signal from a base station and may construct a frozen decode matrix for decoding frozen bits from data of the downlink signal. The device may construct a linear feedback shift register (LFSR) generator matrix for a component of scrambling sequence seed bits and may multiply the frozen decode matrix and the LFSR generator matrix to generate a mapping matrix for mapping a value of a scrambling sequence initialization vector that initializes a scrambler to the frozen bits. The device may determine an inverse matrix of the mapping matrix and may multiply the inverse matrix and the frozen decode matrix to obtain a final matrix. The device may utilize the final matrix to recover, from the data of the downlink signal, the scrambling sequence seed bits used to initialize the component and may perform actions based on the scrambling sequence seed bits.
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