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公开(公告)号：US20240292428A1
公开(公告)日：2024-08-29
申请号：US18170322
申请日：2023-02-16
Applicant: VIAVI Solutions Inc.
Inventor： Matthew David BROWN , Onur DIZDAR , Jiancao HOU , Chi-ming LEUNG , Ata SATTARZADEH HASHEMI , Yi Xien YAP , Wei LI
IPC: H04W72/232 , H04L1/00
CPC classification number: H04W72/232 , H04L1/0038 , H04L1/0061
Abstract: In some implementations, a user equipment (UE) may perform a decoding of downlink control information (DCI) via a physical downlink control channel (PDCCH) based on: a detection, by the UE, of a UE-specific scrambling sequence and a radio network temporary identifier (RNTI) corresponding to the UE-specific scrambling sequence; and a skipping, by the UE, of a de-scrambling operation prior to the decoding of the DCI, wherein information regarding the UE-specific scrambling sequence and the RNTI is not previously stored by the UE. The UE may refrain from decoding a plurality of possible UE-specific scrambling sequences based on the skipping of the de-scrambling operation prior to the decoding of the DCI.
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2.发明公开公开(公告)号：US20240333311A1
公开(公告)日：2024-10-03
申请号：US18128707
申请日：2023-03-30
Applicant: VIAVI Solutions Inc.
Inventor： Onur DIZDAR , Matthew David BROWN , Jiancao HOU , Chi-ming LEUNG , Ata SATTARZADEH HASHEMI , Yi Xien YAP
CPC classification number: H03M13/2778 , H03M13/13 , H03M13/635
Abstract: A device may receive a downlink signal from a base station and may determine an input-output relation of polar encoding based on a vector of the downlink signal. The device may perform an interleaving operation with a matrix and the input-output relation to obtain an interleaved vector and may utilize rate matching with the interleaved vector to determine a scrambling sequence of the downlink signal. The device may utilize a reverse sequence generator with the scrambling sequence to determine a scrambling sequence initialization vector for the scrambling sequence and may perform one or more actions based on the scrambling sequence initialization vector.
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Patent Agency Ranking
公开(公告)号：US20250096820A1
公开(公告)日：2025-03-20
申请号：US18960776
申请日：2024-11-26
Applicant: VIAVI Solutions Inc.
Inventor： Onur DIZDAR , Matthew David BROWN , Jiancao HOU , Chi-ming LEUNG , Ata SATTARZADEH HASHEMI , Yi Xien YAP
Abstract: A device may receive a downlink signal from a base station and may construct a frozen decode matrix for decoding frozen bits from data of the downlink signal. The device may construct a linear feedback shift register (LFSR) generator matrix for a component of scrambling sequence seed bits and may multiply the frozen decode matrix and the LFSR generator matrix to generate a mapping matrix for mapping a value of a scrambling sequence initialization vector that initializes a scrambler to the frozen bits. The device may determine an inverse matrix of the mapping matrix and may multiply the inverse matrix and the frozen decode matrix to obtain a final matrix. The device may utilize the final matrix to recover, from the data of the downlink signal, the scrambling sequence seed bits used to initialize the component and may perform actions based on the scrambling sequence seed bits.
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公开(公告)号：US20240235734A9
公开(公告)日：2024-07-11
申请号：US18048809
申请日：2022-10-21
Applicant: VIAVI Solutions Inc.
Inventor： Jiancao HOU , Wei LI , Matthew David BROWN , Chi-ming LEUNG
CPC classification number: H04L1/0063 , H03M13/13 , H03M13/3776
Abstract: A device may receive a PDCCH signal, may decode encoded bits of the PDCCH signal to generate coded bits, may reencode the coded bits, and may calculate a detection error probability of each coded bit at an output of soft demodulation. The device may calculate a channel decoding error probability that cyclic redundancy check bits are still attached to the coded bits, and may calculate an error probability of channel reencoding, of each coded bit, due to error propagation of polar decoding and reencoding. The device may calculate a probability density of a BMR associated with the coded bits, and may calculate a threshold based on the detection error probability, the channel decoding error probability, the error probability of channel reencoding, and the probability density of a BMR. The device may determine that the PDCCH signal is invalid based on the BMR being greater than the threshold.
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公开(公告)号：US20250070802A1
公开(公告)日：2025-02-27
申请号：US18946175
申请日：2024-11-13
Applicant: VIAVI Solutions Inc.
Inventor： Onur DIZDAR , Matthew David BROWN , Jiancao HOU , Chi-ming LEUNG , Ata SATTARZADEH HASHEMI , Yi Xien YAP
Abstract: A device may receive a downlink signal from a base station and may determine an input-output relation of polar encoding based on a vector of the downlink signal. The device may perform an interleaving operation with a matrix and the input-output relation to obtain an interleaved vector and may utilize rate matching with the interleaved vector to determine a scrambling sequence of the downlink signal. The device may utilize a reverse sequence generator with the scrambling sequence to determine a scrambling sequence initialization vector for the scrambling sequence and may perform one or more actions based on the scrambling sequence initialization vector.
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6.发明公开公开(公告)号：US20240333313A1
公开(公告)日：2024-10-03
申请号：US18128725
申请日：2023-03-30
Applicant: VIAVI Solutions Inc.
Inventor： Onur DIZDAR , Matthew David BROWN , Jiancao HOU , Chi-ming LEUNG , Ata SATTARZADEH HASHEMI , Yi Xien YAP
CPC classification number: H03M13/2927 , H03M13/13 , H03M13/2778
Abstract: A device may receive a downlink signal from a base station and may construct a frozen decode matrix for decoding frozen bits from data of the downlink signal. The device may construct a linear feedback shift register (LFSR) generator matrix for a component of scrambling sequence seed bits and may multiply the frozen decode matrix and the LFSR generator matrix to generate a mapping matrix for mapping a value of a scrambling sequence initialization vector that initializes a scrambler to the frozen bits. The device may determine an inverse matrix of the mapping matrix and may multiply the inverse matrix and the frozen decode matrix to obtain a final matrix. The device may utilize the final matrix to recover, from the data of the downlink signal, the scrambling sequence seed bits used to initialize the component and may perform actions based on the scrambling sequence seed bits.
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公开(公告)号：US20240137153A1
公开(公告)日：2024-04-25
申请号：US18048809
申请日：2022-10-20
Applicant: VIAVI Solutions Inc.
Inventor： Jiancao HOU , Wei LI , Matthew David BROWN , Chi-ming LEUNG
CPC classification number: H04L1/0063 , H03M13/13 , H03M13/3776
Abstract: A device may receive a PDCCH signal, may decode encoded bits of the PDCCH signal to generate coded bits, may reencode the coded bits, and may calculate a detection error probability of each coded bit at an output of soft demodulation. The device may calculate a channel decoding error probability that cyclic redundancy check bits are still attached to the coded bits, and may calculate an error probability of channel reencoding, of each coded bit, due to error propagation of polar decoding and reencoding. The device may calculate a probability density of a BMR associated with the coded bits, and may calculate a threshold based on the detection error probability, the channel decoding error probability, the error probability of channel reencoding, and the probability density of a BMR. The device may determine that the PDCCH signal is invalid based on the BMR being greater than the threshold.
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