公开(公告)号：US20150270233A1

公开(公告)日：2015-09-24

申请号：US14223805

申请日：2014-03-24

Applicant: MICHAEL B. VINCENT ,  TRUNG Q. DUONG ,  ZHIWEI GONG ,  SCOTT M. HAYES ,  ALAN J. MAGNUS ,  DOUGLAS G. MITCHELL ,  EDUARD J. PABST ,  JASON R. WRIGHT ,  WENG F. YAP

Inventor： MICHAEL B. VINCENT ,  TRUNG Q. DUONG ,  ZHIWEI GONG ,  SCOTT M. HAYES ,  ALAN J. MAGNUS ,  DOUGLAS G. MITCHELL ,  EDUARD J. PABST ,  JASON R. WRIGHT ,  WENG F. YAP

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/564 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/014

Abstract: Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.

Abstract translation: 提供了晶片级封装以及用于生产具有防分层再分配层的晶片级封装的方法。 在一个实施例中，该方法包括在半导体管芯上建立内部再分布层。 内部再分布层包括含有金属布线特征的绝缘材料体。 在电介质材料的主体中形成无路由的介质块，并且不被金属布线特征中断。 外再分布层在内再分布层上产生并且包含金属平面，其被图案化以包括覆盖无路由介质块的一个或多个除气开口。 无路由介质块具有最小宽度，长度和深度，每个至少两倍于外再分布层的厚度。

公开(公告)号：US20150145108A1

公开(公告)日：2015-05-28

申请号：US14090975

申请日：2013-11-26

Applicant: WENG F. YAP ,  EDUARD J. PABST

Inventor： WENG F. YAP ,  EDUARD J. PABST

IPC: H01L23/522 ,  H01L23/66 ,  H01L21/768

CPC classification number: H01L23/66 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/181 ,  H01L2924/00

Abstract: Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes producing a plurality of vertically-elongated contacts in ohmic contact with interconnect lines contained within one or more redistribution layers built over the frontside of a semiconductor die. A molded radiofrequency (RF) separation or stand-off layer is formed over the redistribution layers through which the plurality of vertically-elongated contacts extend. An antenna structure is fabricated or otherwise provided over the molded RF stand-off layer and electrically coupled to the semiconductor die through at least one of the plurality of vertically-elongated contacts.

Abstract translation: 提供了用于制造微电子封装的微电子封装和方法。 在一个实施例中，该方法包括产生多个垂直细长的触点，以与在半导体管芯的前侧构建的一个或多个再分布层内所包含的互连线欧姆接触。 在再分配层上形成模制的射频（RF）分离或隔离层，多个垂直细长的触点通过该分配层延伸。 天线结构被制造或以其它方式设置在模制的RF隔离层上并且通过多个垂直细长的触点中的至少一个电连接到半导体管芯。

公开(公告)号：US20150371960A1

公开(公告)日：2015-12-24

申请号：US14310992

申请日：2014-06-20

Applicant: WENG F. YAP ,  ZHIWEI GONG

Inventor： WENG F. YAP ,  ZHIWEI GONG

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00 ,  H01L21/52 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L23/66 ,  H01L21/52 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/6622 ,  H01L2223/6677 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/3025

Abstract: System-in-Packages (SiPs) and methods for producing SiPs are provided. In one embodiment, the above-described SiP fabrication method includes the step or process of forming a through-hole in a core package, the core package containing an electrically-conducive routing feature exposed at a sidewall surface of the through-hole. A leaded component is positioned adjacent the core package such that an elongated lead of the leaded component extends into the through-hole. An electrically-conductive material, such as solder, is then applied into the through hole to electrically couple the elongated lead of the leaded component to the electrically-conductive routing feature of the core package.

Abstract translation: 提供了系统级封装（SiP）和生产SiP的方法。 在一个实施例中，上述SiP制造方法包括在芯组件中形成通孔的步骤或工艺，所述芯组件包含暴露在通孔的侧壁表面处的电导通路径特征。 引线部件邻近芯部封装定位，使得引导部件的细长引线延伸到通孔中。 然后将诸如焊料的导电材料施加到通孔中以将引导部件的细长引线电耦合到芯部封装的导电路由特征。

公开(公告)号：US20150333028A1

公开(公告)日：2015-11-19

申请号：US14277343

申请日：2014-05-14

Applicant: WENG F. YAP ,  ALAN J. MAGNUS

Inventor： WENG F. YAP ,  ALAN J. MAGNUS

IPC: H01L23/00 ,  B23K1/00 ,  B23K1/20

CPC classification number: H01L24/20 ,  B23K1/0016 ,  B23K1/20 ,  B23K3/0623 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L2224/02166 ,  H01L2224/04105 ,  H01L2224/10126 ,  H01L2224/11013 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13016 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/0132

Abstract: Wafer level packages and methods for producing wafer level packages having non-wettable solder collars are provided. In one embodiment, the method includes forming solder mask openings in a solder mask layer exposing regions of a patterned metal level underlying the solder mask layer. Before or after forming solder mask openings in the solder mask layer, non-wettable solder collars are produced extending partially over the exposed regions of the patterned metal level. Solder balls are deposited onto the non-wettable solder collars and into the solder mask openings such that circumferential clearances are provided around base portions of the solder balls and sidewalls of the solder mask layer defining the solder mask openings.

Abstract translation: 提供了晶圆级封装以及用于生产具有不可润湿的焊锡圈的晶片级封装的方法。 在一个实施例中，该方法包括在暴露焊料掩模层下面的图案化金属层的区域的焊料掩模层中形成焊接掩模开口。 在焊料掩模层中形成焊接掩模开口之前或之后，产生部分地在图案化金属层的暴露区域上延伸的不可润湿的焊接套环。 将焊球沉积在不可润湿的焊接环上并进入焊接掩模开口中，使得周边间隙设置在限定焊料掩模开口的焊料球的基部和焊料掩模层的侧壁周围。

公开(公告)号：US20150194388A1

公开(公告)日：2015-07-09

申请号：US14149335

申请日：2014-01-07

Applicant: EDUARD J. PABST ,  SERGIO P. PACHECO ,  WENG F. YAP

Inventor： EDUARD J. PABST ,  SERGIO P. PACHECO ,  WENG F. YAP

IPC: H01L23/552 ,  H01L21/768 ,  H01L23/66 ,  H01L23/522

CPC classification number: H01L23/552 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L2223/6677 ,  H01L2224/12105

Abstract: Shielded device packages and related fabrication methods are provided. An exemplary device package includes one or more electrical components, a molding compound overlying the one or more electrical components, a conductive interconnect structure within the molding compound, a conductive frame structure laterally surrounding the one or more electrical components and the interconnect structure, and a shielding structure overlying the one or more electrical components. The shielding structure is electrically connected to the frame structure and at least a portion of the molding compound resides between the shielding structure and the one or more electrical components.

Abstract translation: 提供了屏蔽器件封装和相关的制造方法。 示例性的器件封装包括一个或多个电气部件，覆盖所述一个或多个电气部件的模制化合物，所述模制化合物内的导电互连结构，横向围绕所述一个或多个电部件和所述互连结构的导电框架结构，以及 覆盖一个或多个电气部件的屏蔽结构。 屏蔽结构电连接到框架结构，并且模制化合物的至少一部分位于屏蔽结构和一个或多个电气部件之间。

公开(公告)号：US20160064341A1

公开(公告)日：2016-03-03

申请号：US14470679

申请日：2014-08-27

Applicant: WENG F. YAP ,  ALAN J. MAGNUS

Inventor： WENG F. YAP ,  ALAN J. MAGNUS

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/03466 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05105 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/96 ,  H01L2924/014 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/00014

Abstract: Microelectronic packages and methods for fabricating microelectronic packages having texturized solder pads, which can improve solder joint reliability, are provided. In one embodiment, the method includes forming a texturized dielectric region having a texture pattern, such as a hatch pattern, in an under-pad dielectric layer. A texturized solder pad is produced over the texturized dielectric region. The texturized solder pad has a solder contact surface to which the texture pattern is transferred such that the area of the solder contact surface is increased relative to a non-texturized solder pad of equivalent dimensions.

Abstract translation: 提供了微电子封装和用于制造具有纹理化焊盘的微电子封装的方法，其可以提高焊点可靠性。 在一个实施例中，该方法包括在下焊盘电介质层中形成具有纹理图案（例如阴影图案）的纹理化电介质区域。 在纹理化电介质区域上产生纹理化的焊盘。 纹理化焊料焊盘具有焊接接触表面，纹理图案被转印到该焊接接触表面，使得焊料接触表面的面积相对于等效尺寸的非变形焊料垫而增加。

公开(公告)号：US20150262981A1

公开(公告)日：2015-09-17

申请号：US14216690

申请日：2014-03-17

Applicant: WENG F. YAP

Inventor： WENG F. YAP

IPC: H01L25/16 ,  H01L23/495 ,  H01L23/12 ,  H05K1/02 ,  H01L23/00 ,  H01L21/78 ,  H05K1/18 ,  H01L21/48 ,  H01L25/18

CPC classification number: H01L25/16 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/12 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49589 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/12105 ,  H01L2224/24175 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/181 ,  H05K1/0284 ,  H05K1/181 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10174 ,  Y10T29/41 ,  Y10T29/49126 ,  Y10T29/49139 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of a method for fabricating System-in-Packages (SiPs) are provided, as are embodiments of a SiP. In one embodiment, the method includes producing a first package including a first molded package body having a sidewall. A first leadframe is embedded within the first molded package body and having a first leadframe lead exposed through the sidewall. In certain implementations, a semiconductor die may also be encapsulated within the first molded package body. A Surface Mount Device (SMD) is mounted to the sidewall of the first molded package body such that a first terminal of the SMD is in ohmic contact with the first leadframe lead exposed through the sidewall.

Abstract translation: 提供了用于制造系统级封装（SiP）的方法的实施例，如SiP的实施例。 在一个实施例中，该方法包括产生包括具有侧壁的第一模制封装主体的第一封装。 第一引线框架嵌入在第一模制封装主体内并且具有通过侧壁暴露的第一引线框引线。 在某些实施方案中，半导体管芯也可以封装在第一模制封装体内。 表面贴装器件（SMD）安装在第一模制封装主体的侧壁上，使得SMD的第一端子与通过侧壁暴露的第一引线框引线欧姆接触。

公开(公告)号：US20150137381A1

公开(公告)日：2015-05-21

申请号：US14086745

申请日：2013-11-21

Applicant: WENG F. YAP ,  SCOTT M. HAYES ,  ALAN J. MAGNUS

Inventor： WENG F. YAP ,  SCOTT M. HAYES ,  ALAN J. MAGNUS

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L24/94 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Microelectronic packages and methods for fabricating microelectronic packages having optical mask layers are provided. In one embodiment, the method includes building redistribution layers over the frontside of a semiconductor die. The redistribution layers includes a body of dielectric material in which a plurality of interconnect lines are formed. An optical mask layer is formed over the frontside of the semiconductor die and at least a portion of the redistribution layers. The optical mask layer has an opacity greater than the opacity of the body of dielectric material and blocks or obscures visual observation of an interior portion of the microelectronic package through the redistribution layers.

Abstract translation: 提供了用于制造具有光学掩模层的微电子封装的微电子封装和方法。 在一个实施例中，该方法包括在半导体管芯的前侧构建再分配层。 再分配层包括其中形成有多条互连线的电介质材料体。 在半导体管芯的前侧和再分布层的至少一部分之间形成光掩模层。 光掩模层具有大于电介体材料的不透明度的不透明度，并阻挡或掩盖通过再分布层对微电子封装的内部的目视观察。

公开(公告)号：US20150061139A1

公开(公告)日：2015-03-05

申请号：US14013923

申请日：2013-08-29

Applicant: WENG F. YAP

Inventor： WENG F. YAP

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L24/26 ,  H01L21/568 ,  H01L21/768 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/83

Abstract: Microelectronic packages and methods for fabricating microelectronic packages are provided. The fabrication method may be carried-out utilizing a preformed panel having a frontside cavity and a backside cavity in which first and second microelectronic devices are positioned, respectively. One or more frontside RDL layers are produced over the frontside of the preformed panel in ohmic contact with or otherwise electrically coupled to the first microelectronic device. Similarly, one or more backside RDL layers are formed over the backside of the preformed panel in ohmic contact with or otherwise electrically coupled to the second microelectronic device. A frontside contact array is produced over the frontside of the preformed panel and electrically coupled to at least the first microelectronic device through the frontside RDL layers. Lastly, the preformed panel is singulated to yield a microelectronic package including a package body in which the first and second microelectronic devices are embedded.

Abstract translation: 提供了用于制造微电子封装的微电子封装和方法。 制造方法可以使用具有分别位于第一和第二微电子器件的前侧空腔和后侧空腔的预成型面板进行。 一个或多个前沿RDL层在预成型面板的前侧上以与第一微电子器件欧姆接触或以其他方式电耦合产生。 类似地，一个或多个背面RDL层以与第二微电子器件欧姆接触或以其他方式电耦合到预成型面板的背面形成。 在预成型面板的前侧产生前端接触阵列，并通过前侧RDL层电耦合到至少第一微电子器件。 最后，将预成型的面板分开以产生包括嵌入第一和第二微电子器件的封装体的微电子封装。

公开(公告)号：US20150162310A1

公开(公告)日：2015-06-11

申请号：US14097459

申请日：2013-12-05

Applicant: MICHAEL B. VINCENT ,  JASON R. WRIGHT ,  WENG F. YAP

Inventor： MICHAEL B. VINCENT ,  JASON R. WRIGHT ,  WENG F. YAP

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/12042 ,  H01L2924/1815 ,  H01L2924/00

Abstract: Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body in an area adjacent to where first and second package surface conductors will be (or have been) formed on both sides of the trench. The method also includes forming the first and second package surface conductors to electrically couple exposed ends of various combinations of device-to-edge conductors. The trench may be formed using laser cutting, drilling, sawing, etching, or another suitable technique. The package surface conductors may be formed by dispensing (e.g., coating, spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispensing) one or more conductive materials on the package body surface between the exposed ends of the device-to-edge conductors.

Abstract translation: 用于形成微电子器件封装的方法的实施例包括在第一和第二封装表面导体将（或已经）形成在沟槽的两侧上的邻近区域中在封装主体的表面上形成沟槽。 该方法还包括形成第一和第二封装表面导体以电耦合器件对边缘导体的各种组合的暴露端。 沟槽可以使用激光切割，钻孔，锯切，蚀刻或其它合适的技术形成。 封装表面导体可以通过在器件 - 表面导体的暴露端之间的封装主体表面上分配（例如，涂覆，喷涂，喷墨印刷，喷雾印刷，模版印刷或针分配）形成一个或多个导电材料， 边缘导体。