公开(公告)号：US10552284B2

公开(公告)日：2020-02-04

申请号：US15478155

申请日：2017-04-03

Applicant: Western Digital Technologies, Inc.

Inventor： Krishanth Skandakumaran ,  Arun Kumar Medapati ,  Sri Rama Namala ,  Ashwin Narasimha ,  Ajith Kumar B

IPC: G06F11/30 ,  G06F1/32 ,  G06F3/06 ,  G06F11/34 ,  G06F13/42 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/329

Abstract: Techniques for controlling power on a PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method for controlling power including providing power to a memory attached via the PCIe interface; monitoring a state of the attached memory; determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold; and stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory.

公开(公告)号：US10725903B2

公开(公告)日：2020-07-28

申请号：US16051370

申请日：2018-07-31

Applicant: Western Digital Technologies, Inc.

Inventor： Ajith Kumar Battaje ,  Tanay Goel ,  Sandeep Sharma ,  Saurabh Manchanda ,  Arun Kumar Medapati

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/1009 ,  G06F16/901

Abstract: A data storage apparatus that includes a storage device and a processor coupled to the storage device. The processor is configured to receive a read request for a first translation table entry associated with a logical block, identify a dump unit associated with the logical block using a hash function, determine a dump group associated with the dump unit, and identify a second translation table entry associated with the dump unit.

公开(公告)号：US10275310B2

公开(公告)日：2019-04-30

申请号：US14642218

申请日：2015-03-09

Applicant: Western Digital Technologies, Inc.

Inventor： Ajith Kumar B ,  Arun Kumar Medapati

IPC: H03M13/00 ,  G06F11/10

Abstract: A storage device may include a non-volatile memory; and a controller. The controller may be configured to store a plurality of blocks of data in the memory, determine exclusive-or (XOR) parity data for the plurality of blocks, and store the XOR parity data in the memory; store a second block of data in the memory. The controller may be further configured to generate updated XOR parity data by at least XORing a first block of the plurality of blocks and the second block of data with the XOR parity data to remove the first block from the XOR parity data and to add the second block to the XOR parity data, and store the updated XOR parity data in the memory.

公开(公告)号：US20180336125A1

公开(公告)日：2018-11-22

申请号：US16051370

申请日：2018-07-31

Applicant: Western Digital Technologies, Inc.

Inventor： Ajith Kumar Battaje ,  Tanay Goel ,  Sandeep Sharma ,  Saurabh Manchanda ,  Arun Kumar Medapati

IPC: G06F12/02 ,  G06F12/1009 ,  G06F17/30

CPC classification number: G06F12/0246 ,  G06F12/1009 ,  G06F16/9024 ,  G06F2212/1016 ,  G06F2212/1056 ,  G06F2212/152 ,  G06F2212/214 ,  G06F2212/657 ,  G06F2212/7201 ,  G06F2212/7202

Abstract: A data storage apparatus that includes a storage device and a processor coupled to the storage device. The processor is configured to receive a read request for a first translation table entry associated with a logical block, identify a dump unit associated with the logical block using a hash function, determine a dump group associated with the dump unit, and identify a second translation table entry associated with the dump unit.