公开(公告)号：US20190121699A1

公开(公告)日：2019-04-25

申请号：US15790368

申请日：2017-10-23

Applicant: Western Digital Technologies, Inc.

Inventor： Inon COHEN ,  Asaf GUETA

IPC: G06F11/14

CPC classification number: G06F11/1438 ,  G06F11/1441 ,  G06F2201/805

Abstract: A method to perform a lossless synchronization software reset is disclosed including provisions for monitoring an arrangement for occurrence of a software reset condition; saving at least one arrangement parameter in a memory in the arrangement; performing at least one software reset on the arrangement; performing a device mount procedure; reading the at least one arrangement parameter in the memory and initializing at least one component according to the at least one arrangement parameter saved in the memory.

公开(公告)号：US20220300211A1

公开(公告)日：2022-09-22

申请号：US17834840

申请日：2022-06-07

Applicant: Western Digital Technologies, Inc.

Inventor： Tomer Tzvi ELIASH ,  Asaf GUETA ,  Inon COHEN ,  Yuval GROSSMAN

IPC: G06F3/06 ,  G06F13/16

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

公开(公告)号：US20200310696A1

公开(公告)日：2020-10-01

申请号：US16903277

申请日：2020-06-16

Applicant: Western Digital Technologies, Inc.

Inventor： Tomer Tzvi ELIASH ,  Asaf GUETA ,  Inon COHEN ,  Yuval GROSSMAN

IPC: G06F3/06 ,  G06F13/16

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

公开(公告)号：US20190361625A1

公开(公告)日：2019-11-28

申请号：US15986744

申请日：2018-05-22

Applicant: Western Digital Technologies, Inc.

Inventor： Tomer Tzvi ELIASH ,  Asaf GUETA ,  Inon COHEN ,  Yuval GROSSMAN

IPC: G06F3/06 ,  G06F13/16

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.