公开(公告)号：US20200097062A1

公开(公告)日：2020-03-26

申请号：US16140448

申请日：2018-09-24

Applicant: Western Digital Technologies, Inc.

Inventor： Alexander BAZARSKY ,  Tomer Tzvi ELIASH ,  Yuval GROSSMAN

IPC: G06F1/32 ,  G06F3/06 ,  G11C16/12

Abstract: Disclosed are systems and methods for efficient power management for storage devices. A method includes receiving a request to transition a flash memory to a first stand-by mode, wherein the flash memory comprises a plurality of dies. The method also includes causing one or more guard dies of the plurality of dies to transition to the first stand-by mode while causing one or more other dies of the plurality of dies to transition to a second stand-by mode, wherein the second stand-by mode is configured to consume less power than the first stand-by mode. The method also includes receiving an input/output (I/O) request for the flash memory. The method also includes causing the I/O request to be performed on the one or more guard dies that are in the first stand-by mode but not in the second stand-by mode.

公开(公告)号：US20200225856A1

公开(公告)日：2020-07-16

申请号：US16245173

申请日：2019-01-10

Applicant: Western Digital Technologies, Inc.

Inventor： Tomer Tzvi ELIASH ,  Alexander BAZARSKY ,  Yuval GROSSMAN

IPC: G06F3/06 ,  G06F11/07

Abstract: Apparatus, media, methods, and systems for data storage systems and methods for optimized scheduling of background management operations. A data storage system may comprise a controller. The controller is configured to determine a timeout value of an adaptive timeout parameter of the data storage system. The controller is configured to determine whether a first host operation is received. The controller is configured to, when the first host operation is not received, determine whether the timeout value satisfies a threshold value. The controller is configured to, when the timeout value satisfies the threshold value, cause one or more background management operations to be executed at the data storage system.

公开(公告)号：US20220300211A1

公开(公告)日：2022-09-22

申请号：US17834840

申请日：2022-06-07

Applicant: Western Digital Technologies, Inc.

Inventor： Tomer Tzvi ELIASH ,  Asaf GUETA ,  Inon COHEN ,  Yuval GROSSMAN

IPC: G06F3/06 ,  G06F13/16

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

公开(公告)号：US20200310696A1

公开(公告)日：2020-10-01

申请号：US16903277

申请日：2020-06-16

Applicant: Western Digital Technologies, Inc.

Inventor： Tomer Tzvi ELIASH ,  Asaf GUETA ,  Inon COHEN ,  Yuval GROSSMAN

IPC: G06F3/06 ,  G06F13/16

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

公开(公告)号：US20190361625A1

公开(公告)日：2019-11-28

申请号：US15986744

申请日：2018-05-22

Applicant: Western Digital Technologies, Inc.

Inventor： Tomer Tzvi ELIASH ,  Asaf GUETA ,  Inon COHEN ,  Yuval GROSSMAN

IPC: G06F3/06 ,  G06F13/16

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.