公开(公告)号：US12062625B2

公开(公告)日：2024-08-13

申请号：US17490279

申请日：2021-09-30

Applicant: Western Digital Technologies, Inc.

Inventor： Hope Chiu ,  Hua Tan ,  Kent Yang ,  Weiting Jiang ,  Jerry Tang ,  Simon Dong ,  Yuequan Shi ,  Rosy Zhao

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/481 ,  H01L21/56 ,  H01L23/3121 ,  H01L25/0657 ,  H01L2225/06506 ,  H01L2225/0651

Abstract: A semiconductor package includes a substrate having a top planar surface and a semiconductor die mounted on the top planar surface of the substrate. Bond wires electrically connect the semiconductor die to the substrate. Flow control dams are integrally formed with the top planar surface of the substrate and each flow control dam protrudes from the top planar surface of the substrate at a location proximate to the bond wires. The flow control dams reduce the occurrence of wire sweep in the bond wires electrically connected to the substrate and semiconductor die.

公开(公告)号：US20230260975A1

公开(公告)日：2023-08-17

申请号：US17670763

申请日：2022-02-14

Applicant: Western Digital Technologies, Inc.

Inventor： Hua Tan ,  Hope Chiu ,  Weiting Jiang ,  Elley Zhang ,  Cong Zhang ,  Simon Dong ,  Jerry Tang ,  Rosy Zhao

IPC: H01L25/10 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1058

Abstract: A semiconductor device package includes a first substrate having an electrical circuit, semiconductor dies stacked one on top of the other, and bond wires electrically connected one to another. The bond wires electrically couple the semiconductor dies to one another and to the electrical circuit. There is a first bond wire having a first portion connected to a first semiconductor die, a second portion connected to a second semiconductor die, and an intermediate portion between the first portion and second portion. The semiconductor device package further includes a molding compound encapsulating the semiconductor dies, and the first and second portions of the first bond wire. The intermediate portion of the first bond wire is exposed along a top planar surface of the molding compound. The semiconductor device package may be used for coupling one or more other semiconductor device packages thereto via the exposed intermediate portion.

公开(公告)号：US20230129628A1

公开(公告)日：2023-04-27

申请号：US17510212

申请日：2021-10-25

Applicant: Western Digital Technologies, Inc.

Inventor： Simon Dong ,  Hope Chiu ,  Weiting Jiang ,  Elley Zhang ,  Kent Yang ,  Hua Tan ,  Jerry Tang ,  Rui Guo

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/538

Abstract: A semiconductor device package includes a multi-layer substrate including a bottom layer and a top layer. One or more dies are mounted on and electrically coupled to the top layer of the substrate. An electromagnetic interference (EMI) shield encapsulates the substrate and the semiconductor dies. A first plurality of conductive stubs is positioned around edges of the top layer of the substrate. Each of the conductive stubs includes an edge portion having a first thickness and in contact with the EMI shield. A second plurality of conductive stubs is positioned around edges of the bottom layer of the substrate. Each of the second plurality of conductive stubs includes an edge portion having a second thickness less than the first thickness and in contact with the EMI shield.

公开(公告)号：US11942459B2

公开(公告)日：2024-03-26

申请号：US17670763

申请日：2022-02-14

Applicant: Western Digital Technologies, Inc.

Inventor： Hua Tan ,  Hope Chiu ,  Weiting Jiang ,  Elley Zhang ,  Cong Zhang ,  Simon Dong ,  Jerry Tang ,  Rosy Zhao

IPC: H01L25/10 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1058

Abstract: A semiconductor device package includes a first substrate having an electrical circuit, semiconductor dies stacked one on top of the other, and bond wires electrically connected one to another. The bond wires electrically couple the semiconductor dies to one another and to the electrical circuit. There is a first bond wire having a first portion connected to a first semiconductor die, a second portion connected to a second semiconductor die, and an intermediate portion between the first portion and second portion. The semiconductor device package further includes a molding compound encapsulating the semiconductor dies, and the first and second portions of the first bond wire. The intermediate portion of the first bond wire is exposed along a top planar surface of the molding compound. The semiconductor device package may be used for coupling one or more other semiconductor device packages thereto via the exposed intermediate portion.

公开(公告)号：US20240304515A1

公开(公告)日：2024-09-12

申请号：US18357211

申请日：2023-07-24

Applicant: Western Digital Technologies, Inc.

Inventor： Xuyi Yang ,  Yiqin Huang ,  Zengyu Zhou ,  Kandy Sun ,  Jerry Tang ,  Gang Liu ,  Cong Zhang ,  Hope Chiu

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/3735 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/50 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/73204 ,  H01L2225/065 ,  H01L2924/1438 ,  H10B80/00

Abstract: A semiconductor package having various thermal dissipation features to dissipate heat. The semiconductor package may include an integrated circuit and a non-volatile storage device. Vias may be formed in the substrate and filled with a thermal conductive material. A pyrolytic graphite sheet overlays a top surface of the substrate and the vias. The pyrolytic graphite sheet defines one or more openings that enable the integrated circuit and the non-volatile storage device to be coupled to the top surface of the substrate. The integrated circuit is covered by another thermal conductive material such as a copper or silver paste. The copper or silver paste also covers a sidewall of the pyrolytic graphite sheet. The semiconductor package is enclosed by molding material and a metal layer. The pyrolytic graphite sheet connects the metal layer and the thermal conductive material overlaying the integrated circuit to form various thermal dissipation paths.

公开(公告)号：US20230102959A1

公开(公告)日：2023-03-30

申请号：US17490279

申请日：2021-09-30

Applicant: Western Digital Technologies, Inc.

Inventor： Hope Chiu ,  Hua Tan ,  Kent Yang ,  Weiting Jiang ,  Jerry Tang ,  Simon Dong ,  Yuequan Shi ,  Rosy Zhao

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

Abstract: A semiconductor package includes a substrate having a top planar surface and a semiconductor die mounted on the top planar surface of the substrate. Bond wires electrically connect the semiconductor die to the substrate. Flow control dams are integrally formed with the top planar surface of the substrate and each flow control dam protrudes from the top planar surface of the substrate at a location proximate to the bond wires. The flow control dams reduce the occurrence of wire sweep in the bond wires electrically connected to the substrate and semiconductor die.