公开(公告)号：US10812089B2

公开(公告)日：2020-10-20

申请号：US16357169

申请日：2019-03-18

Applicant: Xilinx, Inc.

Inventor： Caleb S. Leung ,  Edward Lee ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans

IPC: H03L7/099 ,  H03K19/177 ,  H03L7/08

Abstract: Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit. With the pre-calibration, PLL and/or ILO lock times during rate change in a multi-rate serializer/deserializer (SERDES) link may be advantageously reduced.

公开(公告)号：US09209960B1

公开(公告)日：2015-12-08

申请号：US14550576

申请日：2014-11-21

Applicant: Xilinx, Inc.

Inventor： Caleb S. Leung ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yu Xu ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04L7/00

CPC classification number: H04L7/0337 ,  H04L7/0025

Abstract: A method relates generally to a receiver. In such a method, a check of a clock and data recovery block of the receiver for a metastable state is performed. A phase input to a phase interpolator of the receiver is changed to cause the clock and data recovery block of the receiver to exit the metastable state within a time limit. To check for the metastable state, a phase difference in received data is determined, and the phase difference is determined to be less than a threshold for the clock and data recovery block being in the metastable state.

Abstract translation: 一种方法一般涉及接收机。 在这种方法中，执行用于亚稳态的接收机的时钟和数据恢复块的检查。 接收机的相位内插器的相位输入被改变，以使接收器的时钟和数据恢复块在时间限制内退出亚稳态。 为了检查亚稳态，确定接收数据中的相位差，并且确定相位差小于时钟和数据恢复块处于亚稳态的阈值。

公开(公告)号：US20200304130A1

公开(公告)日：2020-09-24

申请号：US16357169

申请日：2019-03-18

Applicant: Xilinx, Inc.

Inventor： Caleb S. Leung ,  Edward Lee ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans

IPC: H03L7/099 ,  H03L7/08 ,  H03K19/177

Abstract: Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit. With the pre-calibration, PLL and/or ILO lock times during rate change in a multi-rate serializer/deserializer (SERDES) link may be advantageously reduced.

公开(公告)号：US09960902B1

公开(公告)日：2018-05-01

申请号：US15380653

申请日：2016-12-15

Applicant: Xilinx, Inc.

Inventor： Winson Lin ,  Yu Xu ,  Caleb S. Leung ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04L7/00 ,  H04L1/20

CPC classification number: H04L1/205 ,  H03L7/0814 ,  H04L7/0037 ,  H04L7/033 ,  H04L7/0337

Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.

公开(公告)号：US09882703B1

公开(公告)日：2018-01-30

申请号：US15346434

申请日：2016-11-08

Applicant: Xilinx, Inc.

Inventor： Yu Xu ,  Winson Lin ,  Caleb S. Leung ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans ,  Kun-Yung Chang

IPC: H03D3/24 ,  H04L7/00 ,  H04L12/26 ,  H04L7/033

CPC classification number: H04L43/16 ,  H04L7/0025 ,  H04L7/0083 ,  H04L7/033 ,  H04L25/03 ,  H04L43/028

Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data phase and a crossing phase, respectively, of a sampling clock supplied by a phase interpolator in the receiver; generating a phase detect result signal in response to phase detection of the data samples and the crossing samples; filtering the phase detect result signal to generate a phase interpolator code, the phase interpolator generating the sampling clock based on the phase interpolator code; determining an average phase detect result from the phase detect result signal; and adjusting the phase interpolator code in response to the average phase detect result being less than a threshold value.