公开(公告)号：US20250157900A1

公开(公告)日：2025-05-15

申请号：US18515985

申请日：2023-11-21

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Hao Zheng ,  Dongyu Fan ,  Peng Chen ,  Zhong Lv ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

Abstract: In certain aspects, a semiconductor packaging structure includes an interposer structure, which includes an interconnect bridge, a device circuit, a set of conductive elements, and a molding layer. The interconnect bridge includes a stack of conductive layers and dielectric layers that are disposed alternately and an interconnect structure formed in the stack and penetrating at least part of the stack to connect to a conductive layer in the stack. The device circuit is disposed on and coupled to the interconnect bridge. The set of conductive elements is disposed on and coupled to the interconnect bridge. The set of conductive elements is disposed on a periphery of the device circuit. The interconnect structure of the interconnect bridge is connected to at least one conductive element from the set of conductive elements. The molding layer encapsulates the device circuit and the set of conductive elements.

公开(公告)号：US20240387408A1

公开(公告)日：2024-11-21

申请号：US18529960

申请日：2023-12-05

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Wei Xie ,  Dongyu Fan ,  Lei Liu ,  Kun Zhang ,  Wenxi Zhou ,  ZhiLiang Xia

IPC: H01L23/58 ,  H01L21/60

Abstract: Examples of the present application disclose semiconductor devices, fabrication methods of semiconductor devices, and semiconductor apparatus. In one example, the semiconductor device includes a first die, the first die includes a first bonding layer, wherein the first bonding layer includes a first connection structure and a first metal ring, the first metal ring disposed around the first connection structure.

公开(公告)号：US20240379497A1

公开(公告)日：2024-11-14

申请号：US18468439

申请日：2023-09-15

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Hao Zheng ,  Dongyu Fan ,  Lei Liu ,  ZhiLiang Xia ,  ZhongLiang Huo

IPC: H01L23/473 ,  H01L21/768 ,  H01L23/467 ,  H01L23/522 ,  H01L23/528

Abstract: Examples of the present disclosure disclose a memory and a fabrication method thereof, a memory system, and an electronic device. The memory includes a first semiconductor structure and a second semiconductor structure that are bonded to each other; the first semiconductor structure includes a first dielectric layer and a first conductive pillar located in the first dielectric layer; the second semiconductor structure includes a second dielectric layer and a second conductive pillar located in the second dielectric layer; the second conductive pillar is connected with the first conductive pillar; the memory further includes a heat dissipation channel located in at least one of the first dielectric layer or the second dielectric layer, wherein the heat dissipation channel is disposed as being spaced apart from at least one of the first conductive pillar or the second conductive pillar.

公开(公告)号：US20240379578A1

公开(公告)日：2024-11-14

申请号：US18381030

申请日：2023-10-17

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Dongyu Fan ,  Tingting Gao ,  Wei Xie ,  Zhong Lv ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L23/544 ,  H01L21/268 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: According to one aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure may include a first wafer. The first wafer may include a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer. A pointing direction of the first mark may be the same as an extending direction of the first dicing lane. A cleavage plane of the first wafer may be parallel to the pointing direction of the first mark. The pointing direction of the first mark may be an extending direction of a line of symmetry of the first wafer. The semiconductor structure may include a second wafer. The second wafer and the first wafer may be disposed in a stack. The second wafer may be a plurality of memory array chips.

公开(公告)号：US20230422520A1

公开(公告)日：2023-12-28

申请号：US18141274

申请日：2023-04-28

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Dongyu Fan ,  Dongxue Zhao ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo ,  Wei Liu

IPC: H10B80/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H10B41/27 ,  H10B43/27 ,  H10B51/20

CPC classification number: H10B80/00 ,  H01L25/0652 ,  H01L25/18 ,  H01L24/08 ,  H01L28/00 ,  H01L25/50 ,  H10B41/27 ,  H10B43/27 ,  H10B51/20 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1441 ,  H01L2924/14511

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device includes a first semiconductor structure. The first semiconductor structure includes an array of first-type through stack structures in a first region and an array of second-type through stack structures in a second region, and a slit structure separating the array of first-type through stack structures from the array of second-type through stack structures. The 3D memory device further includes a second semiconductor structure. The second semiconductor structure includes a first periphery circuit and a second periphery circuit at different levels. The second semiconductor structure and the first semiconductor structure are bonded together, such that the first periphery circuit is located between the second periphery circuit and the first semiconductor structure.