公开(公告)号：US12302558B2

公开(公告)日：2025-05-13

申请号：US17559181

申请日：2021-12-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhong Zhang ,  Yuhui Han ,  Cuicui Kong ,  Kun Zhang

IPC: H10B41/44 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20

Abstract: A three-dimensional memory includes a stack structure, a dummy structure and a gate line slit. The stack structure includes gate line layers and isolation layers stacked alternatively in the vertical direction. The dummy structure includes a first dummy section and a second dummy section. The gate line slit has one end extending into a gap formed by at least one of the first dummy section or the second dummy section. At least one of the first dummy section and the second dummy section partially overlaps a projection of the gate line slit onto the horizontal plane to realize connection between the dummy structure and the gate line slit.

公开(公告)号：US12295139B2

公开(公告)日：2025-05-06

申请号：US17352244

申请日：2021-06-18

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/35 ,  H10B43/40

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure including interleaved conductive layers and dielectric layers, a doped semiconductor layer, and a channel structure extending through the stack structure and in contact with the doped semiconductor layer. The channel structure includes a composite dielectric film and a semiconductor channel along a first direction. The composite dielectric film includes a gate dielectric portion and a memory portion along a second direction perpendicular to the first direction. A part of the gate dielectric portion faces, along the first direction, one of the conductive layers that is closest to the doped semiconductor layer.

公开(公告)号：US12256540B2

公开(公告)日：2025-03-18

申请号：US17352239

申请日：2021-06-18

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure including interleaved conductive layers and stack dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion and an undoped portion. A part of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. A part of the doped semiconductor layer is in contact with a sidewall of the part of the doped portion of the semiconductor channel that extends beyond the stack structure.

公开(公告)号：US20240407167A1

公开(公告)日：2024-12-05

申请号：US18491603

申请日：2023-10-20

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Kun Zhang ,  Linchun Wu ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: Methods, devices, and systems for three-dimensional (3D) memory devices are provided. In one aspect, a method for forming a three-dimensional (3D) semiconductor device includes: forming a first stack structure including a plurality of alternating sacrificial layers and dielectric layers, the first stack structure having a first region and a second region; forming gate line slits extending through the first stack structure in the first region and the second region; forming a contact via extending to a target sacrificial layer in the second region; forming cavities coupled to the contact via through the gate line slits; and forming conductive layers in replace of the sacrificial layers in the cavities and a contact in the contact via by depositing a conductive material in the contact via and the cavities. The 3D semiconductor device includes a second stack structure having the conductive layers and the dielectric layers.

公开(公告)号：US20240387408A1

公开(公告)日：2024-11-21

申请号：US18529960

申请日：2023-12-05

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Wei Xie ,  Dongyu Fan ,  Lei Liu ,  Kun Zhang ,  Wenxi Zhou ,  ZhiLiang Xia

IPC: H01L23/58 ,  H01L21/60

Abstract: Examples of the present application disclose semiconductor devices, fabrication methods of semiconductor devices, and semiconductor apparatus. In one example, the semiconductor device includes a first die, the first die includes a first bonding layer, wherein the first bonding layer includes a first connection structure and a first metal ring, the first metal ring disposed around the first connection structure.

公开(公告)号：US12136618B2

公开(公告)日：2024-11-05

申请号：US17858695

申请日：2022-07-06

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Linchun Wu ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack comprising interleaved conductive layers and dielectric layers, a plurality of semiconductor layers contacted with each other and located adjacent to the memory stack, a plurality of channel structures each extending vertically through the memory stack and at least one of the semiconductor layers, a source contact in contact with at least one of the semiconductor layers, and a contact pad located on one side of the semiconductor layers that are away from the memory stack.

公开(公告)号：US12114498B2

公开(公告)日：2024-10-08

申请号：US16920218

申请日：2020-07-02

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Linchun Wu ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H01L23/48 ,  H01L21/48 ,  H10B43/27 ,  H01L21/306

CPC classification number: H10B43/27 ,  H01L21/30604 ,  H01L21/30625

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a stop layer, a polysilicon layer, a memory stack including interleaved stack conductive layers and stack dielectric layers, and a plurality of channel structures each extending vertically through the memory stack and the polysilicon layer, stopping at the stop layer.

公开(公告)号：US12089413B2

公开(公告)日：2024-09-10

申请号：US17510752

申请日：2021-10-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yanwei Shi ,  Yanhong Wang ,  Cheng Gan ,  Liang Chen ,  Wei Liu ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC: H10B43/40 ,  G11C16/04 ,  G11C16/24 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/41

CPC classification number: H10B43/40 ,  G11C16/0483 ,  G11C16/24 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/41 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit including a recess gate transistor. The peripheral circuits also include a second peripheral circuit including a flat gate transistor.

公开(公告)号：US12082411B2

公开(公告)日：2024-09-03

申请号：US17020383

申请日：2020-09-14

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Zhong Zhang ,  Lei Liu ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer above and in contact with the plurality of channel structures, a plurality of source contacts above the memory stack and in contact with the semiconductor layer, a plurality of contacts through the semiconductor layer, and a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below and in contact with the source line mesh. A first set of the plurality of contacts are distributed below and in contact with the source line mesh.

公开(公告)号：US12069854B2

公开(公告)日：2024-08-20

申请号：US17480998

申请日：2021-09-21

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun Zhang ,  Yuancheng Yang ,  Wenxi Zhou ,  Wei Liu ,  Zhiliang Xia ,  Liang Chen ,  Yanhong Wang

IPC: H10B41/20 ,  H01L25/065 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC classification number: H10B41/20 ,  H01L25/0652 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a first semiconductor layer, an array of NAND memory strings, and a first peripheral circuit of the array of NAND memory strings. Sources of the array of NAND memory strings are in contact with a first side of the first semiconductor layer. The first peripheral circuit includes a first transistor in contact with a second side of the first semiconductor layer opposite to the first side. The second semiconductor structure includes a second semiconductor layer and a second peripheral circuit of the array of NAND memory strings. The second peripheral circuit includes a second transistor in contact with the second semiconductor layer.