公开(公告)号：US20160323995A1

公开(公告)日：2016-11-03

申请号：US15108405

申请日：2014-05-21

Applicant: ZTE CORPORATION

Inventor： Bi YI ,  Fengchao MA ,  Yonghui REN ,  Wang XIONG ,  Yingxin WANG

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/46 ,  H05K1/11 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/10303 ,  H05K2203/0207 ,  H05K2203/16

Abstract: The present disclosure discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present disclosure, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.

Abstract translation: 本公开公开了一种PCB处理方法和PCB。 该方法包括：分别在构成PCB的多个PCB子板上进行层压处理，以及对最顶层的PCB​​子板进行钻孔和电镀以形成通孔; 并且将多个PCB子板层压在一起以形成PCB，并且对所形成的PCB进行钻孔和电镀以形成用于安装连接器的通孔，其中用于安装连接器的盲孔由通孔形成，并且深度 盲孔大于或等于连接器的信号针的长度。 由于本公开的技术方案，PCB的下层的晶片之间的间隔可以加倍，并且晶片之间的布局空间可以加倍。