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    CONNECTOR FOR IMPLEMENTING MULTI-FACETED INTERCONNECTION
    1.
    发明公开
    CONNECTOR FOR IMPLEMENTING MULTI-FACETED INTERCONNECTION 审中-公开

    公开(公告)号：US20230275023A1

    公开(公告)日：2023-08-31

    申请号：US18143170

    申请日：2023-05-04

    Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

    Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Yejie HONG

    IPC: H01L23/532 ,  H01L23/538 ,  H01L23/00

    CPC classification number: H01L23/53228 ,  H01L23/5386 ,  H01L24/14

    Abstract: In a method of manufacturing a connector, a first copper pillar layer and a sacrificial copper pillar layer are formed on a temporary bearing plate coated with copper, an etch stop layer is applied on the sacrificial copper pillar layer and electroplated to form a second copper pillar layer, insulating materials is laminated to form a first dielectric layer, a first circuit layer is formed on the first dielectric layer, a second copper pillar layer and a sacrificial copper pillar layer are extended on the first circuit layer, and a sacrificial copper layer is formed on the first circuit layer, insulating material is laminated on the first circuit layer to form a second dielectric layer, the temporary bearing plate is removed, a second and third circuit layers are simultaneously formed on the first and second dielectric layers, and the sacrificial copper layer and the sacrificial copper pillar layer are etched.

    SIGNAL-HEAT SEPARATED TMV PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    SIGNAL-HEAT SEPARATED TMV PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20230127494A1

    公开(公告)日：2023-04-27

    申请号：US17821725

    申请日：2022-08-23

    Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

    Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Yejie HONG ,  Gao HUANG

    IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56

    Abstract: A signal-heat separated TMV packaging structure includes an insulating dielectric material, an inner signal line layer arranged in the insulating dielectric material, an outer signal line layer, a heat dissipation metal face and a chip. A first side of the insulating dielectric material is provided with an isolating layer. The outer signal line layer is arranged on a surface of a second side of the insulating dielectric material and is connected with the inner signal line layer through a TMV structure. The heat dissipation metal face is arranged on a surface of the first side of the insulating dielectric material, and is separated from the inner signal line layer. The chip is embedded in the insulating dielectric material, with an active face in electrically-conductive connection with the inner signal line layer and a passive face in heat transfer connection with the heat dissipation metal face.

    CYCLIC COOLING EMBEDDED PACKAGING SUBSTRATE AND MANUFACTURING METHOD THEREOF
    3.
    发明申请
    CYCLIC COOLING EMBEDDED PACKAGING SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20230010115A1

    公开(公告)日：2023-01-12

    申请号：US17664417

    申请日：2022-05-22

    Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

    Inventor： Xianming CHEN ,  Yejie HONG ,  Benxia HUANG ,  Lei FENG

    IPC: H01L23/46 ,  H01L21/48

    Abstract: A cyclic cooling embedded packaging substrate and a manufacturing method thereof are disclosed. The packaging substrate includes a dielectric material body, a chip, a first metal face, a second metal face and a first trace. The dielectric material body is provided with a packaging cavity, the chip is packaged in the packaging cavity, the first metal face is embedded in the dielectric material body, covers and is connected to a heat dissipation face of the chip. The second metal face is embedded in the dielectric material body, connected to a surface of the first metal face, and is provided with a first cooling channel pattern for forming a cooling channel. The first trace is arranged on a surface of the dielectric material body or embedded therein, and is connected with a corresponding terminal on an active face of the chip through a first conductive structure.

    PACKAGED CAVITY STRUCTURE AND MANUFACTURING METHOD THEREOF
    5.
    发明公开
    PACKAGED CAVITY STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20240116752A1

    公开(公告)日：2024-04-11

    申请号：US18377419

    申请日：2023-10-06

    Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

    Inventor： Xianming CHEN ,  Lei FENG ,  Jiangjiang ZHAO ,  Benxia HUANG ,  Gao HUANG ,  Yejie HONG

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00301 ,  B81B7/0061 ,  B81C1/00309 ,  B81B2207/092 ,  B81C2203/0118

    Abstract: A packaged cavity structure includes an embedded packaging frame having a first cavity and a first conductive post respectively penetrating an insulation layer in a height direction, a chipset within the first cavity, a first circuit layer on an upper surface of the embedded packaging frame, a first dielectric layer on the first circuit layer, a second circuit layer on the first dielectric layer, a through-hole penetrating the first dielectric layer and the insulation layer, a third circuit layer on a lower surface of the embedded packaging frame, a support post enclosure on the third circuit layer, and a packaging layer formed along the outside of the support post enclosure. A second cavity communicating with the through-hole is formed between the packaging layer and the lower surface of the embedded packaging frame, and the chipset includes a first chip and a second chip provided in a back-to-back stack.

    CAPACITOR AND INDUCTOR EMBEDDED STRUCTURE AND MANUFACTURING METHOD THEREFOR, AND SUBSTRATE
    7.
    发明公开
    CAPACITOR AND INDUCTOR EMBEDDED STRUCTURE AND MANUFACTURING METHOD THEREFOR, AND SUBSTRATE 审中-公开

    公开(公告)号：US20230197739A1

    公开(公告)日：2023-06-22

    申请号：US17998159

    申请日：2020-07-24

    Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

    Inventor： Xianming CHEN ,  Lei FENG ,  Weiyuan YANG ,  Benxia HUANG ,  Yejie HONG

    IPC: H01L27/13

    CPC classification number: H01L27/13 ,  H01L28/10 ,  H01L28/40

    Abstract: A capacitor and inductor embedded structure and a manufacturing method therefor, and a substrate are disclosed. The method includes: providing a metal plate; sequentially depositing and etching a first protective layer, a thin film dielectric layer, a second protective layer, and an upper electrode layer on an upper surface of the metal plate to form a thin film capacitor and a capacitor upper electrode; pressing an upper dielectric layer to the upper surface of the metal plate, covering the thin film capacitor and the capacitor upper electrode, and etching the metal plate to form a capacitor lower electrode; pressing a lower dielectric layer to a lower surface of the metal plate, and performing drilling on the upper dielectric layer and the lower dielectric layer to form inductor through holes and capacitor electrode through holes; electroplating metal to form an inductor and circuit layers.

    SUBSTRATE MANUFACTURING METHOD, EMBEDDED SUBSTRATE AND SEMICONDUCTOR
    10.
    发明公开
    SUBSTRATE MANUFACTURING METHOD, EMBEDDED SUBSTRATE AND SEMICONDUCTOR 审中-公开

    公开(公告)号：US20240153819A1

    公开(公告)日：2024-05-09

    申请号：US18454022

    申请日：2023-08-22

    Applicant: Zhuhai ACCESS Semiconductor Co., LTD.

    Inventor： Xianming CHEN ,  Gao HUANG ,  Wenjian LIN ,  Yejie HONG ,  Benxia HUANG ,  Juchen HUANG

    IPC: H01L21/768 ,  H01L21/48 ,  H01L23/13 ,  H01L23/14

    CPC classification number: H01L21/76885 ,  H01L21/4828 ,  H01L23/13 ,  H01L23/14

    Abstract: A substrate manufacturing method, an embedded substrate and a semiconductor are disclosed. The method includes: manufacturing a first semi-finished substrate including first circuit layers and a first dielectric layer arranged in staggered and laminated manner; arranging a viscous material layer on the first circuit layer to form a device adhering area; adhering an embedded device on the device adhering area, a pin face of the embedded device facing away from the viscous material layer; laminating a second dielectric layer on the first circuit layer, which covers the viscous material layer and the embedded device; manufacturing a first conductive pillar, a second conductive pillar and a second circuit layer, the first conductive pillar extending through the second dielectric layer and configured for connecting the second circuit layer with the first circuit layer, the second conductive pillar being configured for connecting the embedded device with the second circuit layer.

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