公开(公告)号：US20230282490A1

公开(公告)日：2023-09-07

申请号：US18115043

申请日：2023-02-28

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Jindong FENG ,  Benxia HUANG ,  Gao HUANG ,  Juchen HUANG

IPC: H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L23/49838 ,  H01L24/19 ,  H01L2224/19

Abstract: A carrier plate for preparing a package substrate according to an embodiment includes a dielectric layer, a seed layer in the dielectric layer, and a copper pillar layer on the seed layer. A bottom end of the seed layer is higher than a lower surface of the dielectric layer. A top end of the copper pillar layer is lower than an upper surface of the dielectric layer. The upper and lower surfaces of the dielectric layer are respectively provided with a first metal layer and a second metal layer.

公开(公告)号：US20230145610A1

公开(公告)日：2023-05-11

申请号：US17044087

申请日：2020-05-12

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

Inventor： Xianming CHEN ,  Jindong FENG ,  Benxia HUANG ,  Lei FENG ,  Wenshi WANG

IPC: H01L23/31 ,  H01L23/04 ,  H01L23/29 ,  H01L23/48 ,  H01L23/485 ,  H01L23/36 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3107 ,  H01L23/041 ,  H01L23/293 ,  H01L23/481 ,  H01L23/485 ,  H01L23/36 ,  H01L21/568 ,  H01L21/561 ,  H01L24/96

Abstract: An embedded chip package according to an embodiment of the present application may include at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip.

公开(公告)号：US20240063055A1

公开(公告)日：2024-02-22

申请号：US18221004

申请日：2023-07-12

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Benxia HUANG ,  Lei FENG ,  Jindong FENG ,  Yejie HONG

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/47

CPC classification number: H01L21/76805 ,  H01L21/76832 ,  H01L21/32139 ,  H01L21/0234 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/02645 ,  H01L21/47

Abstract: A method for manufacturing a device embedded packaging structure include laminating a first dielectric material on a copper foil to form a first dielectric layer, and forming a first feature pattern in the first dielectric layer to expose the copper foil, etching the exposed copper foil to form a device opening frame and a via post opening frame to obtain a metal frame, applying an adhesive layer on the metal frame, and mounting a device to the adhesive layer in the device opening frame, laminating a second dielectric material to form a second dielectric layer covering the metal frame and filling the device opening frame and the via post opening frame, forming a via post in the via post opening frame, and forming a first wiring layer and a second wiring layer conductively connected by the via post on the upper and lower surfaces of the second dielectric layer.

公开(公告)号：US20210399400A1

公开(公告)日：2021-12-23

申请号：US17220151

申请日：2021-04-01

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Jindong FENG ,  Yejie HONG

IPC: H01P11/00

Abstract: A method for manufacturing an embedded package structure having an air resonant cavity according to an embodiment includes manufacturing a first substrate including a first insulating layer, a chip embedded in the insulating layer, and a wiring layer on a terminal face of the chip of the first substrate, wherein the wiring layer is provided thereon with an opening revealing the terminal face of the chip; manufacturing a second substrate which comprises a second insulating layer; locally applying a first adhesive layer on the wiring layer such that the opening revealing the terminal face of the chip is not covered; and applying a second adhesive layer on the second substrate; and attaching and curing the first adhesive layer of the first substrate and the second adhesive layer of the second substrate to obtain an embedded package structure having an air resonant cavity on the terminal face of the chip.

公开(公告)号：US20230326765A1

公开(公告)日：2023-10-12

申请号：US18005608

申请日：2021-07-09

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd. ,  NEXPERIA B.V.

Inventor： Xianming CHEN ,  Frank BURMEISTER ,  Lei FENG ,  Yujun ZHAO ,  Benxia HUANG ,  Jinxin YI ,  Jindong FENG ,  Yuan LI ,  Lina JIANG ,  Edward TENA ,  Wenshi WANG

IPC: H01L21/48 ,  H01L21/768 ,  H05K3/34 ,  H05K3/18 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L21/4871 ,  H01L21/4828 ,  H01L21/76871 ,  H05K3/3452 ,  H05K3/181 ,  H01L23/49894

Abstract: A package substrate manufacturing method includes: providing a bearing plate, manufacturing a pattern and depositing metal to form the first circuit layer; manufacturing a pattern on the first circuit layer, depositing and etching metal to form a metal cavity, laminating a dielectric layer on the metal cavity, and performing thinning to expose the metal cavity; removing the bearing plate, etching the metal cavity to expose the cavity, depositing metal on the cavity and the dielectric layer, and performing pattern manufacturing and etching to form a second circuit layer; forming a first and second solder mask layers correspondingly on the first and second circuit layers, and performing pattern manufacturing on the first solder mask layer or the second solder mask layer to form a bonding pad; and cutting the cavity, the first circuit layer, the second circuit layer, the first solder mask layer and the second solder mask layer.

公开(公告)号：US20230154859A1

公开(公告)日：2023-05-18

申请号：US18099107

申请日：2023-01-19

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Jindong FENG ,  Jiangjiang ZHAO ,  Wenshi WANG

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/552 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L23/552 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/49838 ,  H01L23/49861

Abstract: Disclosed are a method for manufacturing a support frame structure and a support frame structure. The support frame structure is used for embedded packaging, and includes: a metal plate comprising a support region and an opening region, at least one upper dielectric hole and at least one lower dielectric hole being formed respectively in upper and lower surfaces of the support region, the upper dielectric hole being communicated with the lower dielectric hole; at least one set of metal pillars comprising an upper metal pillar and a lower metal pillar, the upper metal pillar and the lower metal pillar being vertically connected to upper and lower surfaces of the metal plate, respectively; a dielectric layer comprising an upper dielectric layer and a lower dielectric layer, the upper dielectric layer and the lower dielectric layer being correspondingly formed on the upper surface of the metal plate and the upper dielectric hole and on a lower surface of the metal plate and the lower dielectric hole, respectively; and at least one core embedding cavity arranged in the opening region, running through the dielectric layer and the metal plate, and spaced from the upper dielectric hole and the lower dielectric hole by the dielectric layer.

公开(公告)号：US20220068760A1

公开(公告)日：2022-03-03

申请号：US17411144

申请日：2021-08-25

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Jindong FENG ,  Minxiong LI ,  Shigui XIN ,  Wenshi WANG

IPC: H01L23/40 ,  H01L23/373

Abstract: A circuit prearranged heat dissipation embedded packaging structure according to an embodiment of the present disclosure includes at least one chip and a support frame surrounding the at least one chip. The support frame may include a via pillar passing through the support frame in the height direction, a first wiring layer on a first surface of the support frame, and a heat dissipation layer on the back face of the chip. The first wiring layer is flush with or higher than the first surface, the first wiring layer is in conductive connection with the heat dissipation layer, a gap between the chip and the frame is completely filled with the dielectric material, a second wiring layer is formed on a terminal face of the chip, and the second wiring layer is in conductive connection with the first wiring layer through the via pillar.

公开(公告)号：US20210407921A1

公开(公告)日：2021-12-30

申请号：US16948518

申请日：2020-09-22

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Jindong FENG ,  Benxia HUANG ,  Lei FENG ,  Jiangjiang ZHAO ,  Wenshi WANG

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/367 ,  H01L23/552

Abstract: Disclosed are a method for manufacturing a support frame structure and a support frame structure. The method includes steps of: providing a metal plate including a support region and an opening region; forming an upper dielectric hole and a lower dielectric hole respectively at an upper surface and a lower surface of the support region by photolithography, with a metal spacer connected between the upper dielectric hole and the lower dielectric hole; forming an upper metal pillar on an upper surface of the metal plate, and laminating an upper dielectric layer which covers the upper metal pillar and the upper dielectric hole; etching the metal spacer, forming a lower metal pillar on the lower surface of the metal plate, and laminating a lower dielectric layer which covers the lower metal pillar and the lower dielectric hole.

公开(公告)号：US20240321594A1

公开(公告)日：2024-09-26

申请号：US18612661

申请日：2024-03-21

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

Inventor： Xianming CHEN ,  Xiaowei XU ,  Yejie HONG ,  Benxia HUANG ,  Gao HUANG ,  Dongfeng ZHANG ,  Jindong FENG

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49827 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68345 ,  H01L2224/24155 ,  H01L2224/82106

Abstract: An embedded magnet frame, an integrated structure and a manufacturing method are disclosed. The manufacturing method includes: manufacturing conductive metal columns, a first sacrificial block and a second sacrificial block on a surface of a bearing plate; laminating a first dielectric layer on the surface of the bearing plate so that the first dielectric layer covers the conductive metal columns, the first sacrificial block and the second sacrificial block; thinning the first dielectric layer to expose surfaces of the conductive metal columns, the first sacrificial block and the second sacrificial block; etching the first sacrificial block and the second sacrificial block to form corresponding first and second mounting cavities, the second mounting cavity being used for mounting a chip; filling the first mounting cavity with magnetic slurry to form an embedded magnet; and removing the bearing plate to form an embedded magnet frame.

公开(公告)号：US20230276576A1

公开(公告)日：2023-08-31

申请号：US18174619

申请日：2023-02-25

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

Inventor： Xianming CHEN ,  Wenjian LIN ,  Gao HUANG ,  Lei FENG ,  Jindong FENG ,  Benxia HUANG ,  Zhijun ZHANG

IPC: H05K1/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H05K1/11 ,  H05K3/42 ,  H05K3/10 ,  H05K3/30

CPC classification number: H05K1/186 ,  H01L21/56 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H05K1/113 ,  H05K3/423 ,  H05K3/108 ,  H05K3/305 ,  H01L2224/19 ,  H01L2224/2101 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K3/0023

Abstract: A package substrate and a manufacturing method thereof are disclosed. The method includes: providing an inner substrate; processing an adhesive photosensitive material on a surface of a first side of the inner substrate to obtain an adhesive first insulating dielectric layer; mounting a component on the first insulating dielectric layer; and processing a photosensitive packaging material on the first side of the inner substrate to obtain a second insulating dielectric layer, where the second insulating dielectric layer covers the component.