公开(公告)号：US10332931B2

公开(公告)日：2019-06-25

申请号：US15455055

申请日：2017-03-09

Applicant: ams AG

Inventor： Cathal Cassidy ,  Joerg Siegert ,  Franz Schrank

IPC: H01L27/146 ,  H01L23/00 ,  H01L31/0296

Abstract: The semiconductor device comprises a semiconductor wafer with an integrated circuit, formed by a plurality of dies, a further semiconductor wafer, which differs from the semiconductor wafer in diameter and semiconductor material, the semiconductor wafer and the further semiconductor wafer being bonded to one another by means of a bonding layer, and an electrically conductive contact layer arranged on the further semiconductor wafer opposite to the bonding layer.

公开(公告)号：US09735101B2

公开(公告)日：2017-08-15

申请号：US15283183

申请日：2016-09-30

Applicant: ams AG

Inventor： Cathal Cassidy ,  Martin Schrems ,  Franz Schrank

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532 ,  H01L23/552 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises an annular cavity (18) and a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for three-dimensional integration is offered by this scheme.

公开(公告)号：US09870988B2

公开(公告)日：2018-01-16

申请号：US15691654

申请日：2017-08-30

Applicant: ams AG

Inventor： Cathal Cassidy ,  Martin Schrems ,  Franz Schrank

IPC: H01L21/44 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L23/552

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor substrate is provided with an annular cavity extending from a front side of the substrate to an opposite rear side. A metallization is applied in the annular cavity, thereby forming a through-substrate via and leaving an opening of the annular cavity at the front side. A solder ball is placed above the opening and a reflow of the solder ball is effected, thereby forming a void of the through-substrate via, the void being covered by the solder ball.

公开(公告)号：US09245843B2

公开(公告)日：2016-01-26

申请号：US14373627

申请日：2013-01-16

Applicant: ams AG

Inventor： Jochen Kraft ,  Jordi Teva ,  Cathal Cassidy ,  Günther Koppitsch

IPC: H01L23/528 ,  H01L21/308 ,  H01L23/522 ,  H01L21/768 ,  H01L21/74

CPC classification number: H01L23/5226 ,  H01L21/743 ,  H01L21/76877 ,  H01L21/76898 ,  H01L2224/02372

Abstract: The semiconductor device comprises a substrate (1) of semiconductor material, a contact hole (2) reaching from a surface (10) into the substrate, and a contact metallization (12) arranged in the contact hole, so that the contact metallization forms an internal substrate contact (4) on the semiconductor material at least in a bottom area (40) of the contact hole.

Abstract translation: 半导体器件包括半导体材料的衬底（1），从表面（10）到达衬底的接触孔（2）和布置在接触孔中的接触金属化（12），使得接触金属化形成 至少在所述接触孔的底部区域（40）中的所述半导体材料上的内部衬底接触（4）。

公开(公告)号：US20150129999A1

公开(公告)日：2015-05-14

申请号：US14401499

申请日：2013-04-05

Applicant: ams AG

Inventor： Cathal Cassidy ,  Joerg Siegert ,  Franz Schrank

IPC: H01L27/146 ,  H01L31/0296 ,  H01L23/00

CPC classification number: H01L27/1469 ,  H01L24/32 ,  H01L24/83 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14661 ,  H01L27/14663 ,  H01L27/14696 ,  H01L31/0296 ,  H01L31/02966 ,  H01L2924/14 ,  H01L2924/37001

Abstract: The method of wafer-scale integration of semiconductor devices comprises the steps of providing a semiconductor wafer (1), a further semiconductor wafer (2), which differs from the first semiconductor wafer in at least one of diameter, thickness and semiconductor material, and a handling wafer (3), arranging the further semiconductor wafer on the handling wafer, and bonding the further semiconductor wafer to the semiconductor wafer. The semiconductor device may comprise an electrically conductive contact layer (6) arranged on the further semiconductor wafer (2) and a metal layer connecting the contact layer with an integrated circuit.

Abstract translation: 半导体器件的晶片级整合的方法包括以下步骤：在直径，厚度和半导体材料中的至少一个中提供与第一半导体晶片不同的半导体晶片（1），另外的半导体晶片（2），以及 处理晶片（3），将另外的半导体晶片布置在处理晶片上，并将另外的半导体晶片接合到半导体晶片。 半导体器件可以包括布置在另外的半导体晶片（2）上的导电接触层（6）和连接接触层与集成电路的金属层。

公开(公告)号：US20140367862A1

公开(公告)日：2014-12-18

申请号：US14373627

申请日：2013-01-16

Applicant: ams AG

Inventor： Jochen Kraft ,  Jordi Teva ,  Cathal Cassidy ,  Günther Koppitsch

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/743 ,  H01L21/76877 ,  H01L21/76898 ,  H01L2224/02372

Abstract: The semiconductor device comprises a substrate (1) of semiconductor material, a contact hole (2) reaching from a surface (10) into the substrate, and a contact metallization (12) arranged in the contact hole, so that the contact metallization forms an internal substrate contact (4) on the semiconductor material at least in a bottom area (40) of the contact hole.

Abstract translation: 半导体器件包括半导体材料的衬底（1），从表面（10）到达衬底的接触孔（2）和布置在接触孔中的接触金属化（12），使得接触金属化形成 至少在所述接触孔的底部区域（40）中的所述半导体材料上的内部衬底接触（4）。

公开(公告)号：US09773729B2

公开(公告)日：2017-09-26

申请号：US15283189

申请日：2016-09-30

Applicant: ams AG

Inventor： Cathal Cassidy ,  Martin Schrems ,  Franz Schrank

IPC: H01L21/44 ,  H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532 ,  H01L23/552 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor substrate is provided with a through-substrate via comprising a metallization and an opening. A solder ball is placed on the opening. A reflow of the solder ball is performed in such a way that the solder ball closes the through-substrate via and leaves a void in the through-substrate via.

公开(公告)号：US09608035B2

公开(公告)日：2017-03-28

申请号：US14401499

申请日：2013-04-05

Applicant: ams AG

Inventor： Cathal Cassidy ,  Joerg Siegert ,  Franz Schrank

IPC: H01L27/146 ,  H01L23/00 ,  H01L31/0296

CPC classification number: H01L27/1469 ,  H01L24/32 ,  H01L24/83 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14661 ,  H01L27/14663 ,  H01L27/14696 ,  H01L31/0296 ,  H01L31/02966 ,  H01L2924/14 ,  H01L2924/37001

Abstract: The method of wafer-scale integration of semiconductor devices comprises the steps of providing a semiconductor wafer (1), a further semiconductor wafer (2), which differs from the first semiconductor wafer in at least one of diameter, thickness and semiconductor material, and a handling wafer (3), arranging the further semiconductor wafer on the handling wafer, and bonding the further semiconductor wafer to the semiconductor wafer. The semiconductor device may comprise an electrically conductive contact layer (6) arranged on the further semiconductor wafer (2) and a metal layer connecting the contact layer with an integrated circuit.

公开(公告)号：US09553039B2

公开(公告)日：2017-01-24

申请号：US14359568

申请日：2012-11-07

Applicant: ams AG

Inventor： Cathal Cassidy ,  Martin Schrems ,  Franz Schrank

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/00 ,  H01L23/552 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for three dimensional integration is offered by this scheme.

Abstract translation: 半导体器件包括具有金属化（111）的半导体衬底（10），其具有位于衬底的前侧（20）的上端子层（22）。 金属化从基板的后侧（21）形成从上端子层到后端子层（13）的通孔（23）。 贯通基板通孔包括空隙（101），其可以填充有空气或另一种气体。 焊球（100）在不完全填充的情况下关闭空隙。 该方案提供了用于三维集成的各种互连。

公开(公告)号：US20140339698A1

公开(公告)日：2014-11-20

申请号：US14359568

申请日：2012-11-07

Applicant: ams AG

Inventor： Cathal Cassidy ,  Martin Schrems ,  Franz Schrank

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for three dimensional integration is offered by this scheme.

Abstract translation: 半导体器件包括具有金属化（111）的半导体衬底（10），其具有位于衬底的前侧（20）的上端子层（22）。 金属化从基板的后侧（21）形成从上端子层到后端子层（13）的通孔（23）。 贯通基板通孔包括空隙（101），其可以填充有空气或另一种气体。 焊球（100）在不完全填充的情况下关闭空隙。 该方案提供了用于三维集成的各种互连。