Invention Patent
AT314729T
未知
- Patent Title:
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Application No.: AT01967502Application Date: 2001-09-17
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Publication No.: AT314729TPublication Date: 2006-01-15
- Inventor: BOYD DIANE CATHERINE , BRODSKY STEPHEN BRUCE , HANAFI HUSSEIN IBRAHIM , ROY RONNEN ANDREW
- Applicant: IBM
- Assignee: IBM
- Current Assignee: IBM
- Priority: US67218500 2000-09-28
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/336 ; H01L29/78
Abstract:
A sub-0.1 mum MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.
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