公开(公告)号：WO0227799A3

公开(公告)日：2002-11-21

申请号：PCT/GB0104154

申请日：2001-09-17

Applicant: IBM ,  IBM UK

Inventor： BOYD DIANE CATHERINE ,  BRODSKY STEPHEN BRUCE ,  HANAFI HUSSEIN IBRAHIM ,  ROY RONNEN ANDREW

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66545 ,  Y10S438/926

Abstract: A sub-0.1 mu m MOSFET device having minimum poly depletion, silicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene- gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.

Abstract translation: 利用大马士革栅极工艺提供了具有最小多晶硅耗尽，硅化源极和漏极结以及非常低的薄层电阻多晶硅栅极的0.1微米以下的MOSFET器件，其中源极和漏极注入激活退火和硅化在 伪栅极区，其后被去除并被多晶硅栅极区域替代。

公开(公告)号：EP1356507A4

公开(公告)日：2008-05-21

申请号：EP01996224

申请日：2001-12-30

Applicant: IBM

Inventor： GIEWONT KENNETH J ,  BRODSKY STEPHEN BRUCE ,  CABRAL CYRIL JR ,  DOMENICUCCI ANTHONY G ,  RANSOM CRAIG MITCHELL ,  WANG YUN-YU ,  WILDMAN HORATIO S ,  WONG KWONG HON

IPC: C23C14/06 ,  C23C14/34 ,  H01L21/28 ,  H01L21/285 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/44

CPC classification number: C23C14/0094 ,  C23C14/0641 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855

Abstract: A method is provided for forming a capping layer for a semiconductor structure including a silicide-forming metal (2) overlying silicon (1). According to the invention, a layer of nitride (51) is formed overlying the semiconductor structure and in contact with the silicide-forming metal (2). This layer is formed by sputtering form a target in an ambient characterized by a nitrogen flow less than about 45 sccm. The layer is therefore deficient in nitrogen, so that formation of an oxynitride at a native oxide layer (11) on the silicon is avoided and diffusion between the silicon (1) and the metal (2) is not inhibited.

公开(公告)号：JP2002151690A

公开(公告)日：2002-05-24

申请号：JP2001286248

申请日：2001-09-20

Applicant: IBM

Inventor： BOYD DIANE CATHERINE ,  BRODSKY STEPHEN BRUCE ,  HANAFI HUSSEIN IBRAHIM ,  RONEN ANDREW ROY

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a sub 0.1 μm MOSFET device wherein depletion of polysilicon is minimum, a source junction and a drain junction of silicide are comprised, and a sheet resistance of a poly gate is very low. SOLUTION: A damascen gate process is used wherein, with a dummy gate region provided, the injection/activation annealing and siliciding of a source and drain are performed, and then the dummy gate region is removed and replaced with a polysilicon gate region. Thus, a high-performance sub 0.1 μm MOSFET device is provided in which the sheet resistance of the poly gate is 5 Ω/(square) or below.

公开(公告)号：JPH10294291A

公开(公告)日：1998-11-04

申请号：JP31238297

申请日：1997-11-13

Applicant: IBM

Inventor： BRODSKY STEPHEN BRUCE ,  CONTI RICHARD A ,  SUBBANNA SESHADRI

IPC: C23C16/04 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To prevent deep quenching/encroachment into a silicon region, insufficient attachment, uncontrolled selectivity and irregular structure by reacting fire-resistant halogenide with an exposed surface of a silicon substrate and then reacting it with silicon containing gas and reacting it with hydrogen. SOLUTION: A preliminary adjusted wafer 10 is arranged on a heater base 22 with an electric field through 11 in a fire-resistant gas CVD reactor 20. Gas is supplied from gas supply sources 26, 28, 30, 32, 34 to a shower head 24 and gas 40 is also supplied to a rear. Here, fire-resistant metallic halogenide is reacted with a silicon substrate exposed surface in the existence of inert gas and fire-resistant metal is selectively attached to a silicon substrate exposed surface. Then, fire-resistant metallic halogenide is reacted with silicon containing gas, silicon substrate quenching is limited by fire-resistant metallic halogenide and a thickness of fire-resistant meal is increased. Furthermore, fire-resistant metallic halogenide is reacted with hydrogen and fire-resistant metal is further deposited.

公开(公告)号：DE3785826T2

公开(公告)日：1993-10-28

申请号：DE3785826

申请日：1987-05-05

Applicant: IBM

Inventor： AHN KIE YEUNG ,  BASAVAIAH SARYADEVARA ,  BRODSKY STEPHEN BRUCE ,  CORTELLINO CHARLES ANTHONY ,  LEVINE JOSEPH ELI

IPC: B41C1/14 ,  B41N1/24 ,  H01L21/48 ,  H05K3/12

公开(公告)号：AT314729T

公开(公告)日：2006-01-15

申请号：AT01967502

申请日：2001-09-17

Applicant: IBM

Inventor： BOYD DIANE CATHERINE ,  BRODSKY STEPHEN BRUCE ,  HANAFI HUSSEIN IBRAHIM ,  ROY RONNEN ANDREW

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78

Abstract: A sub-0.1 mum MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.

公开(公告)号：DE3785826D1

公开(公告)日：1993-06-17

申请号：DE3785826

申请日：1987-05-05

Applicant: IBM

Inventor： AHN KIE YEUNG ,  BASAVAIAH SARYADEVARA ,  BRODSKY STEPHEN BRUCE ,  CORTELLINO CHARLES ANTHONY ,  LEVINE JOSEPH ELI

IPC: B41C1/14 ,  B41N1/24 ,  H01L21/48 ,  H05K3/12

公开(公告)号：AU8787701A

公开(公告)日：2002-04-08

申请号：AU8787701

申请日：2001-09-17

Applicant: IBM

Inventor： BRODSKY STEPHEN BRUCE ,  HANAFI HUSSEIN IBRAHIM ,  ROY RONNEN ANDREW

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78 ,  H01L29/00

Abstract: A sub-0.1 mum MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.

公开(公告)号：SG68635A1

公开(公告)日：1999-11-16

申请号：SG1997003565

申请日：1997-09-25

Applicant: IBM

Inventor： BALASUBRAMANYAM KARANAM ,  BRODSKY STEPHEN BRUCE ,  CONTI RICHARD ANTHONY ,  EL-KAREH BADIH

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/43 ,  H01L29/78

Abstract: A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.