公开(公告)号：WO0227799A3

公开(公告)日：2002-11-21

申请号：PCT/GB0104154

申请日：2001-09-17

Applicant: IBM ,  IBM UK

Inventor： BOYD DIANE CATHERINE ,  BRODSKY STEPHEN BRUCE ,  HANAFI HUSSEIN IBRAHIM ,  ROY RONNEN ANDREW

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66545 ,  Y10S438/926

Abstract: A sub-0.1 mu m MOSFET device having minimum poly depletion, silicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene- gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.

Abstract translation: 利用大马士革栅极工艺提供了具有最小多晶硅耗尽，硅化源极和漏极结以及非常低的薄层电阻多晶硅栅极的0.1微米以下的MOSFET器件，其中源极和漏极注入激活退火和硅化在 伪栅极区，其后被去除并被多晶硅栅极区域替代。

公开(公告)号：JP2002151690A

公开(公告)日：2002-05-24

申请号：JP2001286248

申请日：2001-09-20

Applicant: IBM

Inventor： BOYD DIANE CATHERINE ,  BRODSKY STEPHEN BRUCE ,  HANAFI HUSSEIN IBRAHIM ,  RONEN ANDREW ROY

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a sub 0.1 μm MOSFET device wherein depletion of polysilicon is minimum, a source junction and a drain junction of silicide are comprised, and a sheet resistance of a poly gate is very low. SOLUTION: A damascen gate process is used wherein, with a dummy gate region provided, the injection/activation annealing and siliciding of a source and drain are performed, and then the dummy gate region is removed and replaced with a polysilicon gate region. Thus, a high-performance sub 0.1 μm MOSFET device is provided in which the sheet resistance of the poly gate is 5 Ω/(square) or below.

公开(公告)号：JP2001267565A

公开(公告)日：2001-09-28

申请号：JP2001017484

申请日：2001-01-25

Applicant: IBM

Inventor： BOYD DIANE CATHERINE ,  HANAFI HUSSEIN IBRAHIM ,  IEONG MEIKEI ,  NATZLE WESLEY CHARLES

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/302 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/306

Abstract: PROBLEM TO BE SOLVED: To provide a metal oxide film semiconductor field effect type(MOSFET) device, which has a gate insulator of high permittivity (permittivity higher than 7), low overlap capacity (at most 0.35 fF/μm) and a channel length shorter than the gate length as defined by lithography. SOLUTION: This method contains a damascene treatment process and a chemical oxide removal(COR) process. In the COR process, a large tape is formed on a pad oxide layer. When the pad oxide layer is combined with the gate insulator of high permittivity, low overlap capacity, short channel length and superior device characteristic can be realized, as compared with an MOSFET device which is formed by using a normal complementary metal oxide film semiconductor(CMOS) method.

公开(公告)号：JP2001244460A

公开(公告)日：2001-09-07

申请号：JP2001007903

申请日：2001-01-16

Applicant: IBM

Inventor： BOYD DIANE CATHERINE ,  HANAFI HUSSEIN I ,  NATZLE WESLEY CHARLES

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a technique for manufacturing a MOSFET device of 0.05 μm or smaller in size having a super halo doping profile, which provides an excellent short channel characteristic. SOLUTION: This technique utilizes a damascene gate process to obtain a MOSFET structure wherein the thickness of an oxide on source/drain regions is not related to the thickness of a gate oxide and a disposable spacer technique to form a super halo doping profile.

公开(公告)号：AT314729T

公开(公告)日：2006-01-15

申请号：AT01967502

申请日：2001-09-17

Applicant: IBM

Inventor： BOYD DIANE CATHERINE ,  BRODSKY STEPHEN BRUCE ,  HANAFI HUSSEIN IBRAHIM ,  ROY RONNEN ANDREW

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78

Abstract: A sub-0.1 mum MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.