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    METHOD FOR FORMING MOSFET DEVICE
    2.
    发明专利
    METHOD FOR FORMING MOSFET DEVICE 失效

    公开(公告)号：JP2001267565A

    公开(公告)日：2001-09-28

    申请号：JP2001017484

    申请日：2001-01-25

    Applicant: IBM

    Inventor： BOYD DIANE CATHERINE ,  HANAFI HUSSEIN IBRAHIM ,  IEONG MEIKEI ,  NATZLE WESLEY CHARLES

    IPC: H01L29/43 ,  H01L21/28 ,  H01L21/302 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/306

    Abstract: PROBLEM TO BE SOLVED: To provide a metal oxide film semiconductor field effect type(MOSFET) device, which has a gate insulator of high permittivity (permittivity higher than 7), low overlap capacity (at most 0.35 fF/μm) and a channel length shorter than the gate length as defined by lithography. SOLUTION: This method contains a damascene treatment process and a chemical oxide removal(COR) process. In the COR process, a large tape is formed on a pad oxide layer. When the pad oxide layer is combined with the gate insulator of high permittivity, low overlap capacity, short channel length and superior device characteristic can be realized, as compared with an MOSFET device which is formed by using a normal complementary metal oxide film semiconductor(CMOS) method.

    MANUFACTURING METHOD OF MOSFET DEVICE
    3.
    发明专利
    MANUFACTURING METHOD OF MOSFET DEVICE 审中-公开

    公开(公告)号：JP2002151690A

    公开(公告)日：2002-05-24

    申请号：JP2001286248

    申请日：2001-09-20

    Applicant: IBM

    Inventor： BOYD DIANE CATHERINE ,  BRODSKY STEPHEN BRUCE ,  HANAFI HUSSEIN IBRAHIM ,  RONEN ANDREW ROY

    IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To provide a sub 0.1 μm MOSFET device wherein depletion of polysilicon is minimum, a source junction and a drain junction of silicide are comprised, and a sheet resistance of a poly gate is very low. SOLUTION: A damascen gate process is used wherein, with a dummy gate region provided, the injection/activation annealing and siliciding of a source and drain are performed, and then the dummy gate region is removed and replaced with a polysilicon gate region. Thus, a high-performance sub 0.1 μm MOSFET device is provided in which the sheet resistance of the poly gate is 5 Ω/(square) or below.

    4.
    发明专利
    未知

    公开(公告)号：AT314729T

    公开(公告)日：2006-01-15

    申请号：AT01967502

    申请日：2001-09-17

    Applicant: IBM

    Inventor： BOYD DIANE CATHERINE ,  BRODSKY STEPHEN BRUCE ,  HANAFI HUSSEIN IBRAHIM ,  ROY RONNEN ANDREW

    IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78

    Abstract: A sub-0.1 mum MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.

    Self-aligned diffused source vertical transistors with stack capacitors in a 4f-square memory cell array
    5.
    发明专利
    Self-aligned diffused source vertical transistors with stack capacitors in a 4f-square memory cell array 未知

    公开(公告)号：SG67457A1

    公开(公告)日：1999-09-21

    申请号：SG1997004439

    申请日：1997-12-15

    Applicant: IBM

    Inventor： BURNS STUART MCALLISTER JR ,  HANAFI HUSSEIN IBRAHIM

    IPC: H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/02 ,  G11C11/40

    Abstract: A densely packed array of vertical semiconductor devices, having pillars with stack capacitors thereon, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of adjacent bitlines may be isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F2 to be maintained. The array is suitable for Gbit DRAM applications because the stack capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof. In this case, the lower region diffusion may be controlled either to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.

    4F- SQUARE MEMORY CELL HAVING VERTICAL FLOATING- GATE TRANSISTORS WITH SELF- ALIGNED SHALLOW TRENCH ISOLATION
    6.
    发明专利
    4F- SQUARE MEMORY CELL HAVING VERTICAL FLOATING- GATE TRANSISTORS WITH SELF- ALIGNED SHALLOW TRENCH ISOLATION 未知

    公开(公告)号：MY126393A

    公开(公告)日：2006-09-29

    申请号：MYPI9706119

    申请日：1997-12-18

    Applicant: IBM

    Inventor： BURNS STUART MCALLISTER JR ,  HANAFI HUSSEIN IBRAHIM ,  KOCON WALDEMAR WALTER ,  WELSER JEFFERY J

    IPC: H01L29/788 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792

    Abstract: A DENSELY PACKED ARRAY (200, 420, 500, 510, 540, 850) OF VERTICAL SEMICONDUCTOR DEVICES AND METHODS OF MAKING THEREOF ARE DISCLOSED. THE ARRAY HAS COLUMNS OF BITLINES (220, 700, 705) AND ROWS OF WORDLINES (225, 225'). THE GATES (275, 275') OF THE TRANSISTORS ACT AS THE WORDLINES, WHILE THE SOURCE OR DRAIN REGIONS (215, 240, 405, 755, 774) ACTS AS THE BITLINES. THE ARRAY ALSO HAS VERTICAL PILLARS (230), ACTING AS A CHANNEL, FORMED BETWEEN SOURCE AND DRAIN REGIONS. THE SOURCE REGIONS ARE SELF-ALIGNED AND LOCATED BELOW THE PILLARS. THE SOURCE REGIONS OF ADJACENT BITLINES ARE ISOLATED FROM EACH OTHER WITHOUT INCREASING THE CELL SIZE AND ALLOWING A MINIMUM AREA OF APPROXIMATELY 4F2 TO BE MAINTAINED.THE ISOLATED SOURCES ALLOW INDIVIDUAL CELLS (205, 400, 545) TO BE ADDRESSED AND WRITTEN VIA DIRECT TUNNELING, IN BOTH VOLATILE AND NON-VOLATILE MEMORY CELL CONFIGURATIONS. THE SOURCE MAY BE INITIALLY IMPLANTED. ALTERNATIVELY, THE SOURCE MAY BE DIFFUSED BELOW THE PILLARS AFTER FORMING THEREOF. IN THIS CASE, THE SOURCE DIFFUSION MAY BE CONTROLLED EITHER TO FORM FLOATING PILLARS ISOLATED FROM THE UNDERLYING SUBSTRATE (235), OR TO MAINTAIN CONTACT BETWEEN THE PILLARS AND THE SUBSTRATE.(FIG 8)

    SELF- ALIGNED DIFFUSED SOURCE VERTICAL TRANSISTORS WITH STACK CAPACITORS IN A 4F- SQUARE MEMORY CELL ARRAY
    7.
    发明专利
    SELF- ALIGNED DIFFUSED SOURCE VERTICAL TRANSISTORS WITH STACK CAPACITORS IN A 4F- SQUARE MEMORY CELL ARRAY 未知

    公开(公告)号：MY118306A

    公开(公告)日：2004-09-30

    申请号：MYPI9706162

    申请日：1997-12-18

    Applicant: IBM

    Inventor： BURNS STUART MCALLISTER JR ,  HANAFI HUSSEIN IBRAHIM ,  KALTER HOWARD LEO ,  KOCON WALDEMAR WALTER ,  WELSER JEFFREY J

    IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792

    Abstract: A DENSELY PACKED ARRAY (200, 420, 500, 510, 540, 850) OF VERTICAL SEMICONDUCTOR DEVICES, HAVING PILLARS (230) WITH STACK CAPACITORS (520, 520'') THEREON, AND METHODS OF MAKING THEREOF ARE DISCLOSED. THE PILLARS ACT AS TRANSISTOR CHANNELS, AND ARE FORMED BETWEEN UPPER AND LOWER DOPED REGIONS (240, 405). THE LOWER DOPED REGIONS ARE SELF-ALIGNED AND ARE LOCATED BELOW THE PILLARS. THE ARRAY HAS COLUMNS OF BITLINES (220,700, 705) AND ROWS OF WORD LINES (225, 225''). THE LOWER DOPED REGIONS OF ADJACENT BITLINES MAY BE ISOLATED FROM EACH OTHER WITHOUT INCREASING THE CELL SIZE AND ALLOWING A MINIMUM AREA OF APPROXIMATELY 4F2 TO BE MAINTAINED. THE ARRAY IS SUITABLE FOR GBIT DRAM APPLICATIONS BECAUSE THE STACK CAPACITORS DO NOT INCREASE ARRAY AREA. THE ARRAY MAY HAVE AN OPEN BITLINE, A FOLDED, OR AN OPEN/FOLDED ARCHITECTURE WITH DUAL WORDLINES, WHERE TWO TRANSISTORS ARE FORMED ON TOP OF EACH OTHER IN EACH TRENCH. THE LOWER REGIONS MAY BE INITIALLY IMPLANTED. ALTERNATIVE1Y, THE LOWER REGIONS MAY BE DIFFUSED BELOW THE PILLARS AFTER FORMING THEREOF. IN THIS CASE, THE LOWER REGION DIFFUSION MAY BE CONTROLLED EITHER TO FORM FLOATING PILLARS ISOLATED FROM THE UNDERLYING SUBSTRATE, OR TO MAINTAIN CONTACT BETWEEN THE PILLARS AND THE SUBSTRATE. (FIG.8)

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