Invention Patent
- Patent Title: HIGH SPEED BUS TRANSCEIVER WITH FAULT TOLERANT DESIGN FOR HOT PLUGGABLE APPLICATIONS
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Application No.: CA2073105Application Date: 1992-07-03
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Publication No.: CA2073105CPublication Date: 1997-01-21
- Inventor: CHRISTOPHER ROBERT J , DACOSTA DONALD J , DIEPENBROCK JOSEPH C , EPLEY PHILLIP R
- Applicant: IBM
- Assignee: IBM
- Current Assignee: IBM
- Priority: US78380191 1991-10-28
- Main IPC: H04L25/02
- IPC: H04L25/02 ; G06F13/40 ; H03K19/0175 ; H04L25/08 ; H03K19/082
Abstract:
A high-speed data transport system for use in computers, switches, microprocessors or the like includes a low impedance differential bus and a plurality of transceivers connected to the bus. Each of the transceivers is provided with a driver circuit which places data onto the bus and a receiver for accepting data from the bus. The driver includes a pseudo-differential current driving circuit arrangement which sinks current from only one side of the bus while the other side of the differential bus is undisturbed. The receiver includes a differential comparator biased to a preferred output voltage level.
Public/Granted literature
- CA2073105A1 HIGH SPEED BUS TRANSCEIVER WITH FAULT TOLERANT DESIGN FOR HOT PLUGGABLE APPLICATIONS Public/Granted day:1993-04-29
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