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    HIGH SPEED BUS TRANSCEIVER WITH FAULT TOLERANT DESIGN FOR HOT PLUGGABLE APPLICATIONS
    2.
    发明专利
    HIGH SPEED BUS TRANSCEIVER WITH FAULT TOLERANT DESIGN FOR HOT PLUGGABLE APPLICATIONS 未知

    公开(公告)号：CA2178846C

    公开(公告)日：1998-11-17

    申请号：CA2178846

    申请日：1992-07-03

    Applicant: IBM

    Inventor： EPLEY PHILLIP R ,  DACOSTA DONALD J ,  DIEPENBROCK JOSEPH C ,  CHRISTOPHER ROBERT J

    IPC: H04B1/40

    Abstract: A high-speed data transport system for use in computers, switches, microprocessors or the like includes a low impedance differential bus and a plurality of transceivers connected to the bus. Each of the transceivers is provided with a driver circuit which places data onto the bus and a receiver for accepting data from the bus. The driver includes a pseudo-differential current driving circuit arrangement which sinks current from only one side of the bus while the other side of the differential bus is undisturbed. The receiver includes a differential comparator biased to a preferred output voltage level.

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