Invention Patent
ITTO991056D0
未知
- Patent Title:
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Application No.: ITTO991056Application Date: 1999-11-30
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Publication No.: ITTO991056D0Publication Date: 1999-11-30
- Inventor: PAPPALARDO FRANCESCO , GIACALONE BIAGIO , MAMMOLITI FRANCESCO , GANGI EDMONDO
- Applicant: ST MICROELECTRONICS SRL
- Assignee: ST MICROELECTRONICS SRL
- Current Assignee: ST MICROELECTRONICS SRL
- Priority: ITTO991056 1999-11-30
- Main IPC: G06F7/544
- IPC: G06F7/544 ; G06F15/18 ; G06G7/00 ; G06N5/04 ; H03K20060101
Abstract:
The calculation circuit comprises a subtracter having a first and a second input receiving a first and, respectively, a second input datum; a first output supplying a first output datum equal to the difference between the first and the second input datum; and a second output supplying a sign flag indicating the sign of the first output datum; an XOR logic gate having a first input receiving the sign flag, a second input receiving a first logic selection signal assuming a first level for the selection of the logical fuzzy union operation and a second level for the selection of the logical fuzzy intersection operation, and an output supplying a second logic selection signal; and a multiplexer having a first and a second datum input receiving the first and, respectively, the second input datum; a selection input receiving the second selection signal; and an output supplying a second output datum constituted by the first or the second input datum (A, B) as a function of the level assumed by the second selection signal.
Public/Granted literature
- IT1310756B1 Public/Granted day:2002-02-22
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