公开(公告)号：ITTO991056A1

公开(公告)日：2001-05-30

申请号：ITTO991056

申请日：1999-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PAPPALARDO FRANCESCO ,  GIACALONE BIAGIO ,  MAMMOLITI FRANCESCO ,  GANGI EDMONDO

IPC: G06F7/544 ,  G06F15/18 ,  G06G7/00 ,  G06N5/04 ,  H03K20060101

Abstract: The calculation circuit comprises a subtracter having a first and a second input receiving a first and, respectively, a second input datum; a first output supplying a first output datum equal to the difference between the first and the second input datum; and a second output supplying a sign flag indicating the sign of the first output datum; an XOR logic gate having a first input receiving the sign flag, a second input receiving a first logic selection signal assuming a first level for the selection of the logical fuzzy union operation and a second level for the selection of the logical fuzzy intersection operation, and an output supplying a second logic selection signal; and a multiplexer having a first and a second datum input receiving the first and, respectively, the second input datum; a selection input receiving the second selection signal; and an output supplying a second output datum constituted by the first or the second input datum (A, B) as a function of the level assumed by the second selection signal.

公开(公告)号：IT1310756B1

公开(公告)日：2002-02-22

申请号：ITTO991056

申请日：1999-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PAPPALARDO FRANCESCO ,  GIACALONE BIAGIO ,  MAMMOLITI FRANCESCO ,  GANGI EDMONDO

IPC: G06F7/544 ,  G06F15/18 ,  G06G7/00 ,  G06N5/04 ,  H03K20060101

Abstract: The calculation circuit comprises a subtracter having a first and a second input receiving a first and, respectively, a second input datum; a first output supplying a first output datum equal to the difference between the first and the second input datum; and a second output supplying a sign flag indicating the sign of the first output datum; an XOR logic gate having a first input receiving the sign flag, a second input receiving a first logic selection signal assuming a first level for the selection of the logical fuzzy union operation and a second level for the selection of the logical fuzzy intersection operation, and an output supplying a second logic selection signal; and a multiplexer having a first and a second datum input receiving the first and, respectively, the second input datum; a selection input receiving the second selection signal; and an output supplying a second output datum constituted by the first or the second input datum (A, B) as a function of the level assumed by the second selection signal.

公开(公告)号：ITTO991056D0

公开(公告)日：1999-11-30

申请号：ITTO991056

申请日：1999-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PAPPALARDO FRANCESCO ,  GIACALONE BIAGIO ,  MAMMOLITI FRANCESCO ,  GANGI EDMONDO

IPC: G06F7/544 ,  G06F15/18 ,  G06G7/00 ,  G06N5/04 ,  H03K20060101

Abstract: The calculation circuit comprises a subtracter having a first and a second input receiving a first and, respectively, a second input datum; a first output supplying a first output datum equal to the difference between the first and the second input datum; and a second output supplying a sign flag indicating the sign of the first output datum; an XOR logic gate having a first input receiving the sign flag, a second input receiving a first logic selection signal assuming a first level for the selection of the logical fuzzy union operation and a second level for the selection of the logical fuzzy intersection operation, and an output supplying a second logic selection signal; and a multiplexer having a first and a second datum input receiving the first and, respectively, the second input datum; a selection input receiving the second selection signal; and an output supplying a second output datum constituted by the first or the second input datum (A, B) as a function of the level assumed by the second selection signal.