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    4.
    发明专利
    未知

    公开(公告)号：IT1310756B1

    公开(公告)日：2002-02-22

    申请号：ITTO991056

    申请日：1999-11-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PAPPALARDO FRANCESCO ,  GIACALONE BIAGIO ,  MAMMOLITI FRANCESCO ,  GANGI EDMONDO

    IPC: G06F7/544 ,  G06F15/18 ,  G06G7/00 ,  G06N5/04 ,  H03K20060101

    Abstract: The calculation circuit comprises a subtracter having a first and a second input receiving a first and, respectively, a second input datum; a first output supplying a first output datum equal to the difference between the first and the second input datum; and a second output supplying a sign flag indicating the sign of the first output datum; an XOR logic gate having a first input receiving the sign flag, a second input receiving a first logic selection signal assuming a first level for the selection of the logical fuzzy union operation and a second level for the selection of the logical fuzzy intersection operation, and an output supplying a second logic selection signal; and a multiplexer having a first and a second datum input receiving the first and, respectively, the second input datum; a selection input receiving the second selection signal; and an output supplying a second output datum constituted by the first or the second input datum (A, B) as a function of the level assumed by the second selection signal.

    5.
    发明专利
    未知

    公开(公告)号：ITTO991056D0

    公开(公告)日：1999-11-30

    申请号：ITTO991056

    申请日：1999-11-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PAPPALARDO FRANCESCO ,  GIACALONE BIAGIO ,  MAMMOLITI FRANCESCO ,  GANGI EDMONDO

    IPC: G06F7/544 ,  G06F15/18 ,  G06G7/00 ,  G06N5/04 ,  H03K20060101

    Abstract: The calculation circuit comprises a subtracter having a first and a second input receiving a first and, respectively, a second input datum; a first output supplying a first output datum equal to the difference between the first and the second input datum; and a second output supplying a sign flag indicating the sign of the first output datum; an XOR logic gate having a first input receiving the sign flag, a second input receiving a first logic selection signal assuming a first level for the selection of the logical fuzzy union operation and a second level for the selection of the logical fuzzy intersection operation, and an output supplying a second logic selection signal; and a multiplexer having a first and a second datum input receiving the first and, respectively, the second input datum; a selection input receiving the second selection signal; and an output supplying a second output datum constituted by the first or the second input datum (A, B) as a function of the level assumed by the second selection signal.

    6.
    发明专利
    未知

    公开(公告)号：DE69628177D1

    公开(公告)日：2003-06-18

    申请号：DE69628177

    申请日：1996-12-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PAPPALARDO FRANCESCO ,  ARCIDIACONO LILIANA ,  GIACALONE BIAGIO ,  DI BELLA DARIO

    IPC: G06F9/44 ,  G05B13/02 ,  G06N7/02 ,  G06N7/04

    Abstract: The invention relates to a method of coding and storing fuzzy logic rules, and to a circuit architecture for processing such rules. The method provides for at least one inference rule of the IF/THEN type, having a predetermined number of antecedent parts (A,B,C...) of fuzzy variables and at least one consequent part (Z), to be dismembered and stored into memory words (10) to allow of subsequent processing using logic operators of the AND/OR/NOT type. The coding of rules and variables is effected sequentially. Thus, the occupation of memory locations can be minimized. Specifically, the rules are coded through a multi-word description, such that the number of words coding each rule is a varying number dependent on the number of antecedent parts in the rule.

    7.
    发明专利
    未知

    公开(公告)号：ITTO991056A1

    公开(公告)日：2001-05-30

    申请号：ITTO991056

    申请日：1999-11-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PAPPALARDO FRANCESCO ,  GIACALONE BIAGIO ,  MAMMOLITI FRANCESCO ,  GANGI EDMONDO

    IPC: G06F7/544 ,  G06F15/18 ,  G06G7/00 ,  G06N5/04 ,  H03K20060101

    Abstract: The calculation circuit comprises a subtracter having a first and a second input receiving a first and, respectively, a second input datum; a first output supplying a first output datum equal to the difference between the first and the second input datum; and a second output supplying a sign flag indicating the sign of the first output datum; an XOR logic gate having a first input receiving the sign flag, a second input receiving a first logic selection signal assuming a first level for the selection of the logical fuzzy union operation and a second level for the selection of the logical fuzzy intersection operation, and an output supplying a second logic selection signal; and a multiplexer having a first and a second datum input receiving the first and, respectively, the second input datum; a selection input receiving the second selection signal; and an output supplying a second output datum constituted by the first or the second input datum (A, B) as a function of the level assumed by the second selection signal.

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