- Patent Title: Dummy core plus plating resist restrict resin process and structure
-
Application No.: US14995087Application Date: 2016-01-13
-
Publication No.: US10321560B2Publication Date: 2019-06-11
- Inventor: Pui Yin Yu , Mark Zhang , Jiawen Chen
- Applicant: Multek Technologies Limited
- Applicant Address: US CA San Jose
- Assignee: Multek Technologies Limited
- Current Assignee: Multek Technologies Limited
- Current Assignee Address: US CA San Jose
- Agency: Haverstock & Owens LLP
- Priority: CN201510770530 20151112
- Main IPC: H05K1/02
- IPC: H05K1/02 ; H05K1/11 ; H05K3/46 ; H05K3/06 ; H05K3/18 ; H05K1/03

Abstract:
A printed circuit board (PCB) has multiple layers, where select portions of inner layer circuitry, referred to as inner core circuitry, are exposed from the remaining layers. The PCB having an exposed inner core circuitry is formed using a dummy core plus plating resist process. The select inner core circuitry is part of an inner core. The inner core corresponding to the exposed inner core circuitry forms a semi-flexible PCB portion. The semi-flexible PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid. The inner core is common to both the semi-flexible PCB portion and the remaining rigid PCB portion.
Public/Granted literature
- US20170142828A1 DUMMY CORE PLUS PLATING RESIST RESTRICT RESIN PROCESS AND STRUCTURE Public/Granted day:2017-05-18
Information query