An apparatus including a host interface and a registered clock driver interface. The host interface may be configured to receive an enable command from a host. The registered clock driver interface may be configured to perform power management for a dual in-line memory module, generate data for the dual in-line memory module, communicate the data, receive a clock signal and communicate an interrupt signal. The registered clock driver interface may be disabled at power on. The registered clock driver interface may be enabled by in response to the enable command. The apparatus may be implemented as a component on the dual in-line memory module.