Invention Grant
- Patent Title: Method of fabricating a semiconductor device having reduced contact resistance
-
Application No.: US16678526Application Date: 2019-11-08
-
Publication No.: US11195923B2Publication Date: 2021-12-07
- Inventor: Gaurav Thareja , Xuebin Li , Abhishek Dube , Yi-Chiau Huang , Tushar Vidyadhar Mandrekar , Andy Lo , Patricia M. Liu , Sanjay Natarajan , Saurabh Chopra
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L29/40 ; H01L29/417 ; H01L21/02 ; H01L29/08 ; H01L21/67 ; H01L29/66 ; H01L21/285 ; H01L29/45

Abstract:
Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.
Information query
IPC分类: