公开(公告)号：US12297559B2

公开(公告)日：2025-05-13

申请号：US17961463

申请日：2022-10-06

Applicant: Applied Materials, Inc.

Inventor： Abhishek Dube ,  Xuebin Li ,  Hua Chung ,  Flora Fong-Song Chang

IPC: C30B25/18 ,  C23C16/02 ,  C23C16/24 ,  C23C16/54 ,  C23C16/56 ,  C30B29/06 ,  C30B33/12 ,  H01J37/32 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/687

Abstract: Embodiments of the present disclosure generally relate to methods for forming epitaxial layers on a semiconductor device. In one or more embodiments, methods include removing oxides from a substrate surface during a cleaning process, flowing a processing reagent containing a silicon source and exposing the substrate to the processing reagent during an epitaxy process, and stopping the flow of the processing reagent. The method also includes flowing a purging gas and pumping residues from the processing system, stopping the flow of the purge gas, flowing an etching gas and exposing the substrate to the etching gas. The etching gas contains hydrogen chloride and at least one germanium and/or chlorine compound. The method further includes stopping the flow of the at least one compound while continuing the flow of the hydrogen chloride and exposing the substrate to the hydrogen chloride and stopping the flow of the hydrogen chloride.

公开(公告)号：US20210398814A1

公开(公告)日：2021-12-23

申请号：US17348081

申请日：2021-06-15

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. Hung ,  Benjamin Colombeau ,  Abhishek Dube ,  Sheng-Chin Kung ,  Patricia M. Liu ,  Malcolm J. Bevan ,  Johanes F. Swenberg

IPC: H01L21/28 ,  H01L21/02

Abstract: Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

公开(公告)号：US20210134986A1

公开(公告)日：2021-05-06

申请号：US17080519

申请日：2020-10-26

Applicant: Applied Materials, Inc.

Inventor： Steven C. Hung ,  Benjamin Colombeau ,  Abhishek Dube ,  Sheng-Chin Kung ,  Patricia M. Liu ,  Malcolm J. Bevan ,  Johanes Swenberg

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/786

Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include forming a silicon layer over a semiconductor substrate. The semiconductor substrate may include silicon germanium. The methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The methods may include removing the sacrificial oxide. The methods may include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The methods may include forming a high-k dielectric material overlying the oxygen-containing material.

公开(公告)号：US20180158682A1

公开(公告)日：2018-06-07

申请号：US15882939

申请日：2018-01-29

Applicant: Applied Materials, Inc.

Inventor： Abhishek Dube ,  Xuebin Li ,  Yi-Chiau Huang ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/02

CPC classification number: H01L21/02576 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636

Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.

公开(公告)号：US09881790B2

公开(公告)日：2018-01-30

申请号：US15091332

申请日：2016-04-05

Applicant: Applied Materials, Inc.

Inventor： Abhishek Dube ,  Xuebin Li ,  Yi-Chiau Huang ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/02

CPC classification number: H01L21/02576 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636

Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.

公开(公告)号：US09530638B2

公开(公告)日：2016-12-27

申请号：US14870792

申请日：2015-09-30

Applicant: Applied Materials, Inc.

Inventor： Abhishek Dube ,  Hua Chung ,  Jenn-Yue Wang ,  Xuebin Li ,  Yi-Chiau Huang ,  Schubert S. Chu

IPC: H01L21/20 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/7848 ,  H01L29/7851

Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

Abstract translation: 本公开的实施方式一般涉及在外延膜上硅材料外延生长的方法。 在一个实施方案中，该方法包括在半导体鳍片上形成外延膜，其中外延膜包括具有第一面和第二面的顶表面，并且通过交替地在至少外延膜的顶表面上形成外延层 将顶表面暴露于包含一种或多种硅烷的第一前体气体和包含一种或多种氯化硅烷的第二前体气体，其温度为约375℃至约450℃，室压力为约5托至约 20乇

公开(公告)号：US11456178B2

公开(公告)日：2022-09-27

申请号：US17348081

申请日：2021-06-15

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. Hung ,  Benjamin Colombeau ,  Abhishek Dube ,  Sheng-Chin Kung ,  Patricia M. Liu ,  Malcolm J. Bevan ,  Johanes F. Swenberg

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/321 ,  H01L21/8234

Abstract: Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

公开(公告)号：US09768013B2

公开(公告)日：2017-09-19

申请号：US15247586

申请日：2016-08-25

Applicant: Applied Materials, Inc.

Inventor： Abhishek Dube ,  Schubert S. Chu ,  Jessica S. Kachian ,  David Thompson ,  Jeffrey Anthis

IPC: H01L21/02 ,  H01L21/283 ,  H01J37/32 ,  C23C16/455 ,  C23C16/04

CPC classification number: H01L21/0228 ,  C23C16/04 ,  C23C16/45544 ,  H01J37/32009 ,  H01J37/32357 ,  H01J37/32522 ,  H01J37/32899 ,  H01J2237/334 ,  H01L21/02049 ,  H01L21/02057 ,  H01L21/0217 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/283 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/67167 ,  H01L21/67207 ,  H01L21/67745

Abstract: Methods and apparatus for processing a substrate are described herein. Methods for passivating dielectric materials include forming alkyl silyl moieties on exposed surfaces of the dielectric materials. Suitable precursors for forming the alkyl silyl moieties include (trimethylsilyl)pyrrolidine, aminosilanes, and dichlorodimethylsilane, among others. A capping layer may be selectively deposited on source/drain materials after passivation of the dielectric materials. Apparatus for performing the methods described herein include a platform comprising a transfer chamber, a pre-clean chamber, an epitaxial deposition chamber, a passivation chamber, and an atomic layer deposition chamber.

公开(公告)号：US11649560B2

公开(公告)日：2023-05-16

申请号：US16530641

申请日：2019-08-02

Applicant: Applied Materials, Inc.

Inventor： Errol Antonio C Sanchez ,  Mark J. Saly ,  Schubert Chu ,  Abhishek Dube ,  Srividya Natarajan

IPC: H01L21/00 ,  C30B29/54 ,  C07F9/50 ,  H01L29/08 ,  H01L21/02 ,  C30B25/02

CPC classification number: C30B29/54 ,  C07F9/5009 ,  C30B25/02 ,  H01L21/0262 ,  H01L21/02521 ,  H01L29/0843

Abstract: Embodiments generally relate to methods for depositing silicon-phosphorous materials, and more specifically, relate to using silicon-phosphorous compounds in vapor deposition processes (e.g., epitaxy, CVD, or ALD) to deposit silicon-phosphorous materials. In one or more embodiments, a method for forming a silicon-phosphorous material on a substrate is provided and includes exposing the substrate to a deposition gas containing one or more silicon-phosphorous compounds during a deposition process and depositing a film containing the silicon-phosphorous material on the substrate. The silicon-phosphorous compound has the chemical formula [(R3-vHvSi)—(R2-wHwSi)n]xPHyR′z, where each instance of R and each instance of R′ are independently an alkyl or a halogen, n is 0, 1, or 2; v is 0, 1, 2, or 3; w is 0, 1, or 2; x is 1, 2, or 3; y is 0, 1, or 2; z is 0, 1, or 2, and where x+y+z=3.

公开(公告)号：US11309404B2

公开(公告)日：2022-04-19

申请号：US16502555

申请日：2019-07-03

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Tushar Mandrekar ,  Patricia M. Liu ,  Suketu Arun Parikh ,  Matthias Bauer ,  Dimitri R. Kioussis ,  Sanjay Natarajan ,  Abhishek Dube

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/687 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/67 ,  H01L21/677 ,  H01L29/08

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.