Invention Grant
- Patent Title: Staggered dual-side multi-chip interconnect
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Application No.: US17553519Application Date: 2021-12-16
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Publication No.: US11798923B2Publication Date: 2023-10-24
- Inventor: Shuo Zhang , Eric Zhu , Minto Zheng , Michael Zhai , Town Zhang , Jie Ma
- Applicant: NVIDIA Corp.
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA CORP.
- Current Assignee: NVIDIA CORP.
- Current Assignee Address: US CA Santa Clara
- Agency: Rowan TELS LLC
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L25/10 ; H01L25/16 ; H05K1/18
Abstract:
Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.
Public/Granted literature
- US20230197696A1 Staggered Dual-Side Multi-Chip Interconnect Public/Granted day:2023-06-22
Information query
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