公开(公告)号：US11798923B2

公开(公告)日：2023-10-24

申请号：US17553519

申请日：2021-12-16

Applicant: NVIDIA Corp.

Inventor： Shuo Zhang ,  Eric Zhu ,  Minto Zheng ,  Michael Zhai ,  Town Zhang ,  Jie Ma

IPC: H01L23/538 ,  H01L25/10 ,  H01L25/16 ,  H05K1/18

CPC classification number: H01L25/105 ,  H01L23/5386 ,  H01L25/16 ,  H05K1/181 ,  H01L2225/107 ,  H01L2225/1094 ,  H05K2201/10015 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10704

Abstract: Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.

公开(公告)号：US20230411365A1

公开(公告)日：2023-12-21

申请号：US18462259

申请日：2023-09-06

Applicant: NVIDIA Corp.

Inventor： Shuo Zhang ,  Eric Zhu ,  Minto Zheng ,  Michael Zhai ,  Town Zhang ,  Jie Ma

IPC: H01L25/10 ,  H01L25/16 ,  H01L23/538 ,  H05K1/18

CPC classification number: H01L25/105 ,  H01L25/16 ,  H01L23/5386 ,  H05K1/181 ,  H01L2225/1094 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10704 ,  H01L2225/107 ,  H05K2201/10015

Abstract: Layout techniques for circuits on substrates are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between circuits while simultaneously providing for the rapid provision of transient power demands to the circuits. The layout techniques may also enable improved thermal management for the circuits.

公开(公告)号：US20230197696A1

公开(公告)日：2023-06-22

申请号：US17553519

申请日：2021-12-16

Applicant: NVIDIA Corp.

Inventor： Shuo Zhang ,  Eric Zhu ,  Minto Zheng ,  Michael Zhai ,  Town Zhang ,  Jie Ma

IPC: H01L25/10 ,  H01L25/16 ,  H01L23/538 ,  H05K1/18

CPC classification number: H01L25/105 ,  H01L23/5386 ,  H01L25/16 ,  H05K1/181 ,  H01L2225/107 ,  H01L2225/1094 ,  H05K2201/10015 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10704

Abstract: Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.