- Patent Title: Self-aligned method for vertical recess for 3D device integration
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Application No.: US17878457Application Date: 2022-08-01
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Publication No.: US12336274B2Publication Date: 2025-06-17
- Inventor: Jeffrey Smith , Daniel Chanemougame , Lars Liebmann , Paul Gutwin , Subhadeep Kal , Kandabara Tapily , Anton Devilliers
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H10D30/67
- IPC: H10D30/67 ; H01L21/285 ; H10D30/01 ; H10D30/43 ; H10D62/10 ; H10D84/01 ; H10D84/03 ; H10D84/85 ; H10D88/00

Abstract:
Aspects of the present disclosure provide a self-aligned microfabrication method, which can include providing a substrate having vertically arranged first and second channel structures, forming first and second sacrificial contacts to cover ends of the first and second channel structures, respectively, covering the first and second sacrificial contacts with a fill material, recessing the fill material such that the second sacrificial contact is at least partially uncovered while the first sacrificial contact remains covered, replacing the second sacrificial contact with a cover spacer, removing a remaining portion of the first fill material, uncovering the end of the first channel structure, forming a first source/drain (S/D) contact to cover the end of the first channel structure, covering the first S/D contact with a second fill material, uncovering the end of the second channel structure, and forming a second S/D contact at the end of the second channel structure.
Public/Granted literature
- US20230036597A1 SELF-ALIGNED METHOD FOR VERTICAL RECESS FOR 3D DEVICE INTEGRATION Public/Granted day:2023-02-02
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