The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes sequentially forming a first and a second dielectric stacks on a substrate. The first dielectric stack includes a first and a second dielectric layers alternatingly stacked in a first direction perpendicular to the substrate. The second dielectric stack comprises a third and a fourth dielectric layers stacked in the first direction. The method further includes forming an etch-stop layer on the second dielectric stack and forming a gate line slit (GLS) trench spacer to cover a sidewall of the etch-stop layer. The method further includes replacing the fourth and the second dielectric layers with conductive layers through a GLS opening to form a top select gate (TSG) film stack and a film stack of alternating conductive and dielectric layers, respectively.