公开(公告)号：US20240389307A1

公开(公告)日：2024-11-21

申请号：US18458563

申请日：2023-08-30

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Dongxue ZHAO ,  Yuhui HAN ,  Di WANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

IPC: H10B12/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: Examples of the present disclosure disclose a fabrication method of a semiconductor device, a semiconductor device and a memory system. The method includes: providing a stack structure including a device region and a connection region arranged in a first direction, the stack structure including an interlayer insulating layer and a composite material layer alternatively stacked in a second direction, the composite material layer including a bit line in the connection region, and the second direction intersecting the first direction; forming a contact hole in the connection region, the contact hole extending to the bit line from a first side of the stack structure in the second direction; and forming a contact structure connected with bit line in the contact hole.

公开(公告)号：US20240188290A1

公开(公告)日：2024-06-06

申请号：US18082048

申请日：2022-12-15

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Wei XIE ,  Dongyu FAN ,  Di WANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

IPC: H10B43/20 ,  H01L21/28 ,  H01L29/423 ,  H01L29/792

CPC classification number: H10B43/20 ,  H01L29/40117 ,  H01L29/42348 ,  H01L29/7926

Abstract: Memory device and formation method are provided. The memory device includes a stack structure; and a plurality of gate line slit structures vertically extending through the stack structure to divide the stack structure into a plurality of stack portions. The plurality of GLS structures extend along a first direction in a lateral plane of the stack structure and are arranged along a second direction substantially perpendicular to the first direction. Each stack portion is between corresponding adjacent gate line slit structures. At least one edge stack portion, along the second direction of the plurality of stack portions at edge of the stack structure includes a configuration different from a non-edge stack portion of the plurality of stack portions along the second direction.

公开(公告)号：US20250054890A1

公开(公告)日：2025-02-13

申请号：US18927315

申请日：2024-10-25

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Lei LIU ,  Di WANG ,  Wenxi ZHOU ,  Zhihliang XIA

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B12/00

Abstract: A semiconductor device includes a first structure having a first semiconductor layer and a first transistor of a memory cell, a second structure having a second semiconductor layer, a capacitor structure of the memory cell, and a third dielectric stack formed therein, and bonding structures formed between the first structure and the second structure. The bonding structures are configured to couple the first transistor to the capacitor structure to form the memory cell.

公开(公告)号：US20210265295A1

公开(公告)日：2021-08-26

申请号：US17113557

申请日：2020-12-07

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Lei LIU ,  Di WANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A semiconductor device is provided. The semiconductor device includes a first wafer having an array transistor formed therein, and a second wafer having a capacitor structure formed therein. The semiconductor device also includes a bonding interface formed between the first wafer and second wafer that includes a plurality of bonding structures. The bonding structures are configured to couple the array transistor to the capacitor structure to form a memory cell.

公开(公告)号：US20240413009A1

公开(公告)日：2024-12-12

申请号：US18809015

申请日：2024-08-19

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Ling XU ,  Di WANG ,  Zhong ZHANG ,  Wenxi ZHOU

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/535

Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method includes disposing an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate; and forming a staircase structure and a dividing wall in the alternating dielectric stack. The staircase structure and the dividing wall extend in a second direction parallel to the substrate, and the dividing wall is adjacent to the staircase structure. The method also includes forming, sequentially on the staircase structure, a first barrier layer and a second barrier layer different from the first barrier layer. The method further includes forming a gate line slit (GLS) opening in the dividing wall. The GLS opening penetrates through the alternating dielectric stack in the first direction and is distant from the second barrier layer in a third direction that is parallel to the substrate and is perpendicular to the second direction.

公开(公告)号：US20230363138A1

公开(公告)日：2023-11-09

申请号：US17738661

申请日：2022-05-06

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Yuancheng YANG ,  Dongxue ZHAO ,  Tao YANG ,  Lei LIU ,  Di WANG ,  Kun ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

IPC: H01L27/108

CPC classification number: H01L27/10802

Abstract: Embodiments of three-dimensional memory devices are disclosed. A disclosed memory structure comprises a memory cell comprising: a cylindrical body having a cylindrical shape, an insulating layer surrounding the cylindrical body, a word line contact coupled to a word line and surrounding a first portion of the insulating layer, and multiple plate line contact segments coupled to multiple plate lines respectively and surrounding a second portion of the insulating layer. The memory structure further comprises a bit line contact coupled to a bit line and coupled to a first end of the cylindrical body, a source line contact coupled to a source line, and a source cap coupled between the source line contact and a second end of the cylindrical body to increase a distance between the source line contact and the plate line contact segments.

公开(公告)号：US20230326892A1

公开(公告)日：2023-10-12

申请号：US18336097

申请日：2023-06-16

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Lei LIU ,  Di WANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H10B12/00

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2924/1436 ,  H10B12/0335 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H10B12/30

Abstract: A semiconductor device is provided. The semiconductor device includes a first wafer having an array transistor formed therein, and a second wafer having a capacitor structure formed therein. The semiconductor device also includes a bonding interface formed between the first wafer and second wafer that includes a plurality of bonding structures. The bonding structures are configured to couple the array transistor to the capacitor structure to form a memory cell.

公开(公告)号：US20220366985A1

公开(公告)日：2022-11-17

申请号：US17709651

申请日：2022-03-31

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Di WANG ,  Wenxi ZHOU ,  Tingting ZHAO ,  Zhiliang XIA

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528

Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes sequentially forming a first and a second dielectric stacks on a substrate. The first dielectric stack includes a first and a second dielectric layers alternatingly stacked in a first direction perpendicular to the substrate. The second dielectric stack comprises a third and a fourth dielectric layers stacked in the first direction. The method further includes forming an etch-stop layer on the second dielectric stack and forming a gate line slit (GLS) trench spacer to cover a sidewall of the etch-stop layer. The method further includes replacing the fourth and the second dielectric layers with conductive layers through a GLS opening to form a top select gate (TSG) film stack and a film stack of alternating conductive and dielectric layers, respectively.

公开(公告)号：US20210384219A1

公开(公告)日：2021-12-09

申请号：US17190601

申请日：2021-03-03

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Di WANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Yonggang YANG ,  Kun ZHANG ,  Hao ZHANG ,  Yiming AI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L23/00

Abstract: Aspects of the disclosure provide a semiconductor device and a method for fabricating the same. The method for fabricating the semiconductor device can include forming a stack of alternating first insulating layers and first sacrificial layers over a semiconductor substrate, and forming a staircase in the stack having a plurality of steps, with at least a first step of the staircase including a first sacrificial layer of the first sacrificial layers over a first insulating layer of the first insulating layers. Further, the method can include forming a recess in the first sacrificial layer, forming a second sacrificial layer in the recess, and replacing a portion of the first sacrificial layer and the second sacrificial layer with a conductive material that forms a contact pad.

公开(公告)号：US20230354599A1

公开(公告)日：2023-11-02

申请号：US17731524

申请日：2022-04-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Tao Yang ,  Dongxue ZHAO ,  Yuancheng YANG ,  Lei LIU ,  Kun ZHANG ,  Di WANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528

CPC classification number: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/5283

Abstract: A three-dimensional (3D) memory device includes a first memory cell, a second memory cell, a control gate between the first and second memory cells, a top contact coupled to the first memory cell, and a bottom contact coupled to the second memory cell. The first memory cell can include a first pillar, a first insulating layer surrounding the first pillar, a first gate contact coupled to a first word line, and a second gate contact coupled to a first plate line. The second memory cell can include a second pillar, a second insulating layer surrounding the second pillar, a third gate contact coupled to a second word line, and a fourth gate contact coupled to a second plate line. The 3D memory device can utilize dynamic flash memory (DFM), increase storage density, provide multi-cell storage, provide a three-state logic, decrease leakage current, increase retention time, and decrease refresh rates.