公开(公告)号：US20250157906A1

公开(公告)日：2025-05-15

申请号：US18399626

申请日：2023-12-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Hao ZHENG ,  Dongyu FAN ,  Tingting GAO ,  Lei LIU ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H10B80/00

Abstract: Systems, devices, and methods for fabricating semiconductor structures for semiconductor packaging are provided. One example method includes forming a stack of conductive layers interleaved with isolating layers in a redistribution layer (RDL) structure of a semiconductor device. First contact structures and second contact structures are formed in the RDL structure, where each of the first contact structures extends through a portion of the conductive layers and the isolating layers and is connected to a pad on a first interface of the RDL structure, each of the second contact structures is connected to a respective one of the first contact structures through one of the conductive layers, and each of the second contact structures is connected to a pad on a second interface of the RDL structure opposite to the first interface.

公开(公告)号：US20240339402A1

公开(公告)日：2024-10-10

申请号：US18382251

申请日：2023-10-20

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhong ZHANG ,  Kun ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device includes a stack structure and a first beam structure. The memory device includes array regions and an intermediate region arranged between the array regions in a first lateral direction. The stack structure includes a first block and a second block arranged in a second lateral direction. Each of the first block and the second block includes a wall-structure region. In the intermediate region, the wall-structure regions of the first block and the second block are separated by a staircase structure. The first beam structure is located in the intermediate region and extends along the second lateral direction. The first beam structure is connected to the wall-structure regions of the first block and the second block. The first beam structure includes first dielectric layers and electrode layers that are alternately stacked.

公开(公告)号：US20240282673A1

公开(公告)日：2024-08-22

申请号：US18643322

申请日：2024-04-23

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Linchun WU ,  Kun ZHANG ,  Zhong ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L23/48 ,  H01L21/48 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L23/481 ,  H01L21/4814 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes an insulating layer, a conductive layer stacking with the insulating layer and including a first conductive sublayer and a second conductive sublayer, a memory stack disposed on a side of the conductive layer away from the insulating layer, a spacer structure through the conductive layer, a contact structure in the spacer structure and extending vertically through the insulating layer, and a channel structure including a semiconductor channel. The contact structure includes a first contact portion and a second contact portion in contact with each other. A lateral cross-sectional area of the second contact portion is greater than a lateral cross-sectional area of the first contact portion. A portion of the semiconductor channel is in contact with the first conductive sublayer. The second conductive sublayer is disposed between the first conductive sublayer and the memory stack.

公开(公告)号：US20240164107A1

公开(公告)日：2024-05-16

申请号：US18147555

申请日：2022-12-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： DongXue ZHAO ,  Tao YANG ,  Wenxi ZHOU ,  Yuancheng YANG ,  ZhiLiang XIA ,  ZongLiang HUO

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H01L27/11597 ,  H01L27/1159

Abstract: The present disclosure provides a memory device that includes a film stack having functional tiers stacked in a first direction. Each functional tier includes a first dielectric layer and a conductive layer. The memory device also includes channel structures disposed in an array core region, wherein each channel structure extends through the film stack in the first direction. Each channel structure includes a control gate in a center, a memory film that is disposed on a sidewall of the control gate and includes a ferroelectric film. Each channel structure also includes a channel layer disposed on a sidewall of the memory film.

公开(公告)号：US20230354599A1

公开(公告)日：2023-11-02

申请号：US17731524

申请日：2022-04-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Tao Yang ,  Dongxue ZHAO ,  Yuancheng YANG ,  Lei LIU ,  Kun ZHANG ,  Di WANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528

CPC classification number: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/5283

Abstract: A three-dimensional (3D) memory device includes a first memory cell, a second memory cell, a control gate between the first and second memory cells, a top contact coupled to the first memory cell, and a bottom contact coupled to the second memory cell. The first memory cell can include a first pillar, a first insulating layer surrounding the first pillar, a first gate contact coupled to a first word line, and a second gate contact coupled to a first plate line. The second memory cell can include a second pillar, a second insulating layer surrounding the second pillar, a third gate contact coupled to a second word line, and a fourth gate contact coupled to a second plate line. The 3D memory device can utilize dynamic flash memory (DFM), increase storage density, provide multi-cell storage, provide a three-state logic, decrease leakage current, increase retention time, and decrease refresh rates.

公开(公告)号：US20230354578A1

公开(公告)日：2023-11-02

申请号：US17731523

申请日：2022-04-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Di WANG ,  Lei LIU ,  Yuancheng YANG ,  Wenxi ZHOU ,  Kun ZHANG ,  Tao YANG ,  Dongxue ZHAO ,  Zhiliang XIA ,  Zongliang HUO

IPC: H01L27/108

CPC classification number: H01L27/10802

Abstract: A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact surrounding a first portion of the insulating layer, and a second gate contact surrounding a second portion of the insulating layer. The pillar can be configured to store an electrical charge. The pillar can be a monocrystalline material. The 3D memory device can utilize dynamic flash memory (DFM), decrease defects, increase manufacturing efficiency, decrease leakage current, decrease junction current, decrease power consumption, increase storage density, increase charge retention times, and decrease refresh rates.

公开(公告)号：US20230197507A1

公开(公告)日：2023-06-22

申请号：US17580051

申请日：2022-01-20

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Ling XU ,  Di WANG ,  Zhong ZHANG ,  Wenxi ZHOU

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/528

CPC classification number: H01L21/76832 ,  H01L23/535 ,  H01L23/5283 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895

Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method includes disposing an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate; and forming a staircase structure and a dividing wall in the alternating dielectric stack. The staircase structure and the dividing wall extend in a second direction parallel to the substrate, and the dividing wall is adjacent to the staircase structure. The method also includes forming, sequentially on the staircase structure, a first barrier layer and a second barrier layer different from the first barrier layer. The method further includes forming a gate line slit (GLS) opening in the dividing wall. The GLS opening penetrates through the alternating dielectric stack in the first direction and is distant from the second barrier layer in a third direction that is parallel to the substrate and is perpendicular to the second direction.

公开(公告)号：US20220037490A1

公开(公告)日：2022-02-03

申请号：US17500340

申请日：2021-10-13

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhongwang SUN ,  Zhong ZHANG ,  Lei LIU ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L29/423 ,  H01L27/11529 ,  H01L21/28 ,  H01L27/11573

Abstract: Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

公开(公告)号：US20210366917A1

公开(公告)日：2021-11-25

申请号：US16900511

申请日：2020-06-12

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhongwang SUN ,  Rui SU ,  Zhong ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582

Abstract: Memory device includes a bottom-select-gate (BSG) structure including cut slits vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. A first gate-line slit is between first and second finger regions and includes gate-line sub-slits. The first finger region is divided into a first string region and a second string region by a first cut-slit, formed in the first finger region along a second lateral direction and further extended into at least the second finger region along the first lateral direction. At least one BSG defined by the first cut-slit is located in at least the second finger region to connect to cell strings in the first string region through an inter-portion between adjacent gate-line sub-slits.

公开(公告)号：US20210287991A1

公开(公告)日：2021-09-16

申请号：US16875180

申请日：2020-05-15

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhongwang SUN ,  Zhong ZHANG ,  Wenxi ZHOU ,  Lei LIU ,  Zhiliang XIA

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/321 ,  H01L21/768

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.