Method of forming semiconductor structure

Invention Grant

US08980703B2 Method of forming semiconductor structure 有权

Title translation: 形成半导体结构的方法

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Patent Title: Method of forming semiconductor structure
Patent Title (中): 形成半导体结构的方法
Application No.: US14505510

Application Date: 2014-10-03
Publication No.: US08980703B2

Publication Date: 2015-03-17
Inventor: Chen-Chiu Hsu , Tung-Ming Lai , Kai-An Hsueh , Ming-De Huang
Applicant: Maxchip Electronics Corp.
Applicant Address: TW Hsinchu
Assignee: Maxchip Electronics Corp.
Current Assignee: Maxchip Electronics Corp.
Current Assignee Address: TW Hsinchu
Agency: Jianq Chyun IP Office
Priority: TW100129230A 20110816
Main IPC: H01L21/84
IPC: H01L21/84 ; H01L29/78 ; H01L29/76 ; H01L29/66 ; H01L49/02 ; H01L27/115

Method of forming semiconductor structure

Abstract:

A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract(Chinese):

提供一种形成半导体结构的方法。提供具有单元区域和周边区域的基板。在单元区域中的基板上形成包括栅极氧化物层，浮置栅极和第一间隔物的层叠结构，并且在周边区域的基板上形成电阻体。在堆叠结构旁边的衬底中形成至少两个掺杂区域。介电材料层和导电材料层依次形成在基板上。在衬底上形成图案化的光致抗蚀剂层以覆盖堆叠结构和电阻器的一部分。除去图案化的光致抗蚀剂层未被覆盖的电介质材料层和导电材料层，以在叠层结构上形成栅极间电介质层和控制栅极，同时在电阻器上形成自对准硅化物阻挡层。

Public/Granted literature

US20150024562A1 METHOD OF FORMING SEMICONDUCTOR STRUCTURE Public/Granted day:2015-01-22

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/84	.....衬底不是半导体的，例如绝缘体