公开(公告)号：US20150024562A1

公开(公告)日：2015-01-22

申请号：US14505510

申请日：2014-10-03

Applicant: Maxchip Electronics Corp.

Inventor： Chen-Chiu Hsu ,  Tung-Ming Lai ,  Kai-An Hsueh ,  Ming-De Huang

IPC: H01L29/66 ,  H01L27/115 ,  H01L49/02

CPC classification number: H01L29/66825 ,  H01L27/11517 ,  H01L27/11526 ,  H01L28/20

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract translation: 提供一种形成半导体结构的方法。 提供具有单元区域和周边区域的基板。 在单元区域中的基板上形成包括栅极氧化物层，浮置栅极和第一间隔物的层叠结构，并且在周边区域的基板上形成电阻体。 在堆叠结构旁边的衬底中形成至少两个掺杂区域。 介电材料层和导电材料层依次形成在基板上。 在衬底上形成图案化的光致抗蚀剂层以覆盖堆叠结构和电阻器的一部分。 除去图案化的光致抗蚀剂层未被覆盖的电介质材料层和导电材料层，以在叠层结构上形成栅极间电介质层和控制栅极，同时在电阻器上形成自对准硅化物阻挡层。

公开(公告)号：US08980703B2

公开(公告)日：2015-03-17

申请号：US14505510

申请日：2014-10-03

Applicant: Maxchip Electronics Corp.

Inventor： Chen-Chiu Hsu ,  Tung-Ming Lai ,  Kai-An Hsueh ,  Ming-De Huang

IPC: H01L21/84 ,  H01L29/78 ,  H01L29/76 ,  H01L29/66 ,  H01L49/02 ,  H01L27/115

CPC classification number: H01L29/66825 ,  H01L27/11517 ,  H01L27/11526 ,  H01L28/20

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract translation: 提供一种形成半导体结构的方法。 提供具有单元区域和周边区域的基板。 在单元区域中的基板上形成包括栅极氧化物层，浮置栅极和第一间隔物的层叠结构，并且在周边区域的基板上形成电阻体。 在堆叠结构旁边的衬底中形成至少两个掺杂区域。 介电材料层和导电材料层依次形成在基板上。 在衬底上形成图案化的光致抗蚀剂层以覆盖堆叠结构和电阻器的一部分。 除去图案化的光致抗蚀剂层未被覆盖的电介质材料层和导电材料层，以在叠层结构上形成栅极间电介质层和控制栅极，同时在电阻器上形成自对准硅化物阻挡层。